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// 

//
//  FRAME GEN
//
//
//
//  Description: This module is a pattern generator to test the Aurora
//               designs in hardware. It generates data and passes it 
//               through the Aurora channel. If connected to a framing 
//               interface, it generates frames of varying size and 
//               separation. LFSR is used to generate the pseudo-random 
//               data and lower bits of LFSR are connected to REM bus 

`timescale 1 ns / 1 ps
`define DLY #1

module aurora_8b10b_1_FRAME_GEN
(
    // User Interface
    TX_D,  
    TX_SRC_RDY_N,
    TX_DST_RDY_N,

    // System Interface
    USER_CLK,       
    RESET,
    CHANNEL_UP
); 
//*****************************Parameter Declarations****************************

//***********************************Port Declarations*******************************

   // User Interface
    output  [0:31]     TX_D;
    output             TX_SRC_RDY_N;
    input              TX_DST_RDY_N;

      // System Interface
    input              USER_CLK;
    input              RESET; 
    input              CHANNEL_UP;

//***************************External Register Declarations***************************

    reg                TX_SRC_RDY_N;

//***************************Internal Register Declarations*************************** 

    reg     [0:15]     data_lfsr_r;    
    
    wire               reset_c;


//*********************************Main Body of Code**********************************

  //Generate RESET signal when Aurora channel is not ready
  assign reset_c = RESET || !CHANNEL_UP;

    //______________________________ Transmit Data  __________________________________    
    //Transmit data when TX_DST_RDY_N is asserted. 
    //Random data is generated using XNOR feedback LFSR
    //TX_SRC_RDY_N is asserted on every cycle with data
    always @(posedge USER_CLK)
        if(reset_c)
        begin
            data_lfsr_r          <=  `DLY    16'hABCD;  //random seed value
            TX_SRC_RDY_N    <=  `DLY    1'b1;    
        end
        else if(!TX_DST_RDY_N)
        begin
            data_lfsr_r          <=  `DLY    {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]}, 
                                data_lfsr_r[0:14]};
            TX_SRC_RDY_N    <=  `DLY    1'b0;
        end
    
    //Connect TX_D to the DATA LFSR register
    assign  TX_D    =   {2{data_lfsr_r}};
    

endmodule
