METRICS = [
    'GRBM_GUI_ACTIVE',
    # L1 perfmon
    'TCP_TOTAL_CACHE_ACCESSES_sum',
    'TCP_TCC_READ_REQ_sum',
    'TCP_TCC_WRITE_REQ_sum',
    'TCP_TCC_ATOMIC_WITH_RET_REQ_sum',
    'TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum',
    'TCP_TCC_READ_REQ_LATENCY_sum',
    'TCP_TCC_WRITE_REQ_LATENCY_sum',
    'TCP_TOTAL_ACCESSES_sum',
    'TA_TOTAL_WAVEFRONTS_sum',
    'TCP_GATE_EN1_sum',
    'TCP_GATE_EN2_sum',

    # L2 perfmon
    'TCC_REQ_sum',
    'TCC_HIT_sum',
    'TCC_MISS_sum',
    'TCC_BUSY_sum', 
    'TCC_EA_RDREQ_LEVEL_sum',
    'TCC_EA_WRREQ_LEVEL_sum',
    'TCC_EA_RDREQ_sum',
    'TCC_EA_WRREQ_sum',
    'TCC_EA_ATOMIC_LEVEL_sum',
    'TCC_EA_ATOMIC_sum',
    'TCC_EA0_RDREQ_LEVEL_sum',
    'TCC_EA0_WRREQ_LEVEL_sum',
    'TCC_EA0_RDREQ_sum',
    'TCC_EA0_WRREQ_sum',
    'TCC_EA0_ATOMIC_LEVEL_sum',
    'TCC_EA0_ATOMIC_sum',

    # HBM perfmon
    'TCC_EA_RDREQ_32B_sum',
    'TCC_EA_RDREQ_sum',
    'TCC_EA_WRREQ_64B_sum',
    'TCC_EA_WRREQ_sum',
    'TCC_EA0_RDREQ_sum',
    'TCC_BUBBLE_sum',
    'TCC_EA0_RDREQ_32B_sum',
    'TCC_EA0_WRREQ_64B_sum',
    'TCC_EA0_WRREQ_sum',

    # Flops perfmon
    'SQ_INSTS_VALU_INT32',
    'SQ_INSTS_VALU_INT64',
    'SQ_INSTS_VALU_ADD_F16',
    'SQ_INSTS_VALU_MUL_F16',
    'SQ_INSTS_VALU_TRANS_F16',
    'SQ_INSTS_VALU_FMA_F16',
    'SQ_INSTS_VALU_ADD_F32',
    'SQ_INSTS_VALU_MUL_F32',
    'SQ_INSTS_VALU_TRANS_F32',
    'SQ_INSTS_VALU_FMA_F32',
    'SQ_INSTS_VALU_ADD_F64',
    'SQ_INSTS_VALU_MUL_F64',
    'SQ_INSTS_VALU_TRANS_F64',
    'SQ_INSTS_VALU_FMA_F64',
    'SQ_INSTS_VALU_MFMA_MOPS_F16',
    'SQ_INSTS_VALU_MFMA_MOPS_BF16',
    'SQ_INSTS_VALU_MFMA_MOPS_F32',
    'SQ_INSTS_VALU_MFMA_MOPS_F64',

    # IPC perfmon
    'SQ_INSTS',
    'SQ_BUSY_CU_CYCLES',

    # LDS perfmon
    'SQ_INSTS_LDS',
    'SQ_LDS_BANK_CONFLICT',
    'SQ_LDS_IDX_ACTIVE',
    'SPI_RA_LDS_CU_FULL_CSN',

    # Wave stats perfmon
    'SPI_CSN_WAVE',
    'SQ_INSTS',
    'SQ_WAVES',
    'SQ_WAVE_CYCLES',
    'SQ_WAIT_ANY',
    'SQ_WAIT_INST_ANY',
    'SQ_ACTIVE_INST_ANY',
    'SQ_ACCUM_PREV_HIRES_WAVES',

    # SPI perfmon
    'GRBM_SPI_BUSY',
    'SPI_RA_RES_STALL_CSN',
    'SPI_RA_TMP_STALL_CSN',
    'SPI_RA_WAVE_SIMD_FULL_CSN',
    'SPI_RA_VGPR_SIMD_FULL_CSN',
    'SPI_RA_SGPR_SIMD_FULL_CSN',
    'SPI_RA_LDS_CU_FULL_CSN',
    'SPI_RA_BAR_CU_FULL_CSN',
    'SPI_RA_TGLIM_CU_FULL_CSN',
    'SPI_RA_WVLIM_STALL_CSN',

    # Instruction mix perfmon
    'SQ_INSTS_VALU',
    'SQ_INSTS_MFMA',
    'SQ_INSTS_VMEM',
    'SQ_INSTS_FLAT_LDS_ONLY',
    'SQ_INSTS_LDS',
    'SQ_INSTS_SALU',
    'SQ_INSTS_SMEM',
    'SQ_INSTS_BRANCH',
]
