{M : Type u_3} →
  {inst : AddZeroClass M} →
    {P : Sort u} →
      {toAddSubsemigroup : AddSubsemigroup M} →
        {zero_mem' : 0 ∈ toAddSubsemigroup.carrier} →
          {toAddSubsemigroup' : AddSubsemigroup M} →
            {zero_mem'' : 0 ∈ toAddSubsemigroup'.carrier} →
              { toAddSubsemigroup := toAddSubsemigroup, zero_mem' := zero_mem' } =
                  { toAddSubsemigroup := toAddSubsemigroup', zero_mem' := zero_mem'' } →
                (toAddSubsemigroup ≍ toAddSubsemigroup' → P) → P