The

Potential

of

the

Cell

Processor

for

Scientific

Computing

The

slowing

pace

of

commodity

microprocessor

performance

improvements

combined

with

ever-increasing

chip

power

demands

has

become

of

utmost

concern

to

computational

scientists

As

a

result

the

high

performance

computing

community

is

examining

alternative

architectures

that

address

the

limitations

of

modern

cache-based

designs

In

this

work

we

examine

the

potential

of

using

the

forthcoming

STI

Cell

processor

as

a

building

block

for

future

high-end

computing

systems

Our

work

contains

several

novel

contributions

First

we

introduce

a

performance

model

for

Cell

and

apply

it

to

several

key

scientific

computing

kernels

dense

matrix

multiply

sparse

matrix

vector

multiply

stencil

computations

and

FFTs

The

difficulty

of

programming

Cell

which

requires

assembly

level

intrinsics

for

the

best

performance

makes

this

model

useful

as

an

initial

step

in

algorithm

design

and

evaluation

Next

we

validate

the

accuracy

of

our

model

by

comparing

results

against

published

hardware

results

as

well

as

our

own

implementations

on

the

Cell

full

system

simulator

Additionally

we

compare

Cell

performance

to

benchmarks

run

on

leading

superscalar

-LRB-

AMD

Opteron

-RRB-

VLIW

-LRB-

Intel

-RRB-

and

vector

-LRB-

Cray

-RRB-

architectures

Our

work

also

explores

several

different

mappings

of

the

kernels

and

demonstrates

a

simple

and

effective

programming

model

for

Cell

's

unique

architecture

Finally

we

propose

modest

microarchitectural

modifications

that

could

significantly

increase

the

efficiency

of

double-precision

calculations

Overall

results

demonstrate

the

tremendous

potential

of

the

Cell

architecture

for

scientific

computations

in

terms

of

both

raw

performance

and

power

efficiency

C.

-LSB-

Processor

Architectures

-RSB-

Multiple

Data

Stream

Architectures

Single-instruction

stream

multiple-data-stream

processors

-LRB-

SIMD

-RRB-

Copyright

Association

for

Computing

Machinery

ACM

acknowledges

that

this

contribution

was

authored

or

co-authored

by

a

contractor

or

affiliate

of

the

U.S.

Government

As

such

the

Government

retains

a

nonex-clusive

royalty-free

right

to

publish

or

reproduce

this

article

or

to

allow

others

to

do

so

for

Government

purposes

only

CF

May

Ischia

Italy

Copyright

ACM

C.

-LSB-

Processor

Architectures

-RSB-

Other

Architecture

Styles

Heterogeneous

-LRB-

hybrid

-RRB-

systems

C.

-LSB-

Processor

Architectures

-RSB-

Parallel

Architectures

C.

-LSB-

Performance

of

Systems

-RSB-

Design

studies

modeling

techniques

performance

attributes

D.

-LSB-

Programming

Techniques

-RSB-

Concurrent

Programming

Parallel

Programming

Performance

Design

Over

the

last

decade

the

HPC

community

has

moved

towards

machines

composed

of

commodity

microprocessors

as

a

strategy

for

tracking

the

tremendous

growth

in

processor

performance

in

that

market

As

frequency

scaling

slows

and

the

power

requirements

of

these

mainstream

processors

continues

to

grow

the

HPC

community

is

looking

for

alternative

architectures

that

provide

high

performance

on

scientific

applications

yet

have

a

healthy

market

outside

the

scientific

community

In

this

work

we

examine

the

potential

of

the

forthcoming

STI

Cell

processor

as

a

building

block

for

future

high-end

computing

systems

by

investigating

performance

across

several

key

scientific

computing

kernels

dense

matrix

multiply

sparse

matrix

vector

multiply

stencil

computations

on

regular

grids

as

well

as

and

FFTs

Cell

combines

the

considerable

floating

point

resources

required

for

demanding

numerical

algorithms

with

a

power-efficient

software-controlled

memory

hierarchy

Despite

its

radical

departure

from

previous

mainstream/commodity

processor

designs

Cell

is

particularly

compelling

because

it

will

be

produced

at

such

high

volumes

that

it

will

be

cost-competitive

with

commodity

CPUs

The

current

implementation

of

Cell

is

most

often

noted

for

its

extremely

high

performance

single-precision

-LRB-

SP

-RRB-

arithmetic

which

is

widely

considered

insufficient

for

the

majority

of

scientific

applications

Although

Cell

's

peak

double

precision

performance

is

still

impressive

relative

to

its

commodity

peers

-LRB-

Gflop/s

GHz

-RRB-

we

explore

how

modest

hardware

changes

could

significantly

improve

performance

for

computationally

intensive

DP

applications

This

paper

presents

several

novel

results

We

present

quantitative

performance

data

for

scientific

kernels

that

compares

Cell

performance

to

leading

superscalar

-LRB-

AMD

Opteron

-RRB-

VLIW

-LRB-

Intel

-RRB-

and

vector

-LRB-

Cray

-RRB-

architectures

We

believe

this

study

examines

the

broadest

array

of

scientific

algorithms

to

date

on

Cell

We

developed

both

analytical

models

and

lightweight

simulators

to

predict

kernel

performance

that

we

demonstrated

to

be

accurate

when

compared

against

published

Cell

hardware

result

as

well

as

our

own

implementations

on

the

Cell

full

system

simulator

Our

work

also

explores

the

complexity

of

mapping

several

important

scientific

algorithms

onto

the

Cell

's

unique

architecture

in

order

to

leverage

the

large

number

of

available

functional

units

and

the

software-controlled

memory

Additionally

we

propose

modest

microarchitectural

modifications

that

could

increase

the

efficiency

of

double-precision

arithmetic

calculations

and

demonstrate

significant

performance

improvements

compared

with

the

current

Cell

implementation

Overall

results

demonstrate

the

tremendous

potential

of

the

Cell

architecture

for

scientific

computations

in

terms

of

both

raw

performance

and

power

efficiency

We

also

conclude

that

Cell

's

heterogeneous

multi-core

implementation

is

inherently

better

suited

to

the

HPC

environment

than

homogeneous

commodity

multicore

processors

One

of

the

key

limiting

factors

for

computational

performance

is

off-chip

memory

bandwidth

Since

increasing

the

off-chip

bandwidth

is

prohibitively

expensive

many

architects

are

considering

ways

of

using

available

bandwidth

more

efficiently

Examples

include

hardware

multithreading

or

more

efficient

alternatives

to

conventional

cache-based

architectures

such

as

software-controlled

memories

Software-controlled

memories

can

potentially

improve

memory

subsystem

performance

by

supporting

finely

controlled

prefetch-ing

and

more

efficient

cache-utilization

policies

that

take

advantage

of

application-level

information

but

do

so

with

far

less

architectural

complexity

than

conventional

cache

architectures

While

placing

data

movement

under

explicit

software

control

increases

the

complexity

of

the

programming

model

prior

research

has

demonstrated

that

this

approach

can

be

more

effective

for

hiding

memory

latencies

-LRB-

including

cache

misses

and

TLB

misses

-RRB-

requiring

far

smaller

cache

sizes

to

match

the

performance

of

conventional

cache

implementations

-LSB-

-RSB-

The

performance

of

software-controlled

memory

is

more

predictable

thereby

making

it

popular

for

real-time

embedded

applications

where

guaranteed

response

rates

are

essential

Over

the

last

five

years

a

plethora

of

alternatives

to

conventional

cache-based

architectures

have

been

suggested

including

scratchpad

memories

-LSB-

-RSB-

paged

on-chip

memories

-LSB-

-RSB-

and

explicit

three-level

memory

architectures

-LSB-

-RSB-

Until

recently

few

of

these

architectural

concepts

made

it

into

mainstream

processor

designs

but

the

increasingly

stringent

power/performance

requirements

for

embedded

systems

have

resulted

in

a

number

of

recent

implementations

that

have

adopted

these

concepts

Chips

like

the

Sony

Emotion

Engine

-LSB-

-RSB-

and

Intel

's

both

achieved

high

performance

at

low

power

by

adopting

three

levels

-LRB-

registers

local

memory

external

DRAM

-RRB-

of

software-managed

memory

More

recently

the

STI

Cell

processor

has

adopted

a

similar

approach

where

data

movement

between

SPE

KB

PPC

KB

memo

ry

con

troller

I/O

I/O

EIB

rings

core

cycle

GB/s

SPE

KB

SPE

KB

SPE

KB

SPE

KB

SPE

KB

SPE

KB

SPE

KB

Figure

Overview

of

the

Cell

processor

these

three

address

spaces

is

explicitly

controlled

by

the

application

For

predictable

data

access

patterns

the

local

store

approach

is

highly

advantageous

as

it

can

be

very

efficiently

utilized

through

explicit

software-controlled

scheduling

Improved

bandwidth

utilization

through

deep

pipelining

of

memory

requests

requires

less

power

and

has

a

faster

access

time

than

a

large

cache

due

in

part

to

its

lower

complexity

If

however

the

data

access

pattern

lacks

predictabil-ity

then

the

advantages

of

software-managed

memory

are

lost

This

more

aggressive

approach

to

memory

architecture

was

adopted

to

meet

the

demanding

cost/performance

and

real-time

responsiveness

requirements

of

Sony

's

upcoming

video

game

console

However

to

date

an

in-depth

study

to

evaluate

the

potential

of

utilizing

the

Cell

architecture

in

the

context

of

scientific

computations

does

not

appear

in

the

literature

Cell

-LSB-

-RSB-

was

designed

by

a

partnership

of

Sony

Toshiba

and

IBM

-LRB-

STI

-RRB-

to

be

the

heart

of

Sony

's

forthcoming

gaming

system

Cell

takes

a

radical

departure

from

conventional

multiprocessor

or

multi-core

architectures

Instead

of

using

identical

cooperating

commodity

processors

it

uses

a

conventional

high

performance

PowerPC

core

that

controls

eight

simple

SIMD

cores

called

synergistic

processing

elements

-LRB-

SPEs

-RRB-

where

each

SPE

contains

a

synergistic

processing

unit

-LRB-

SPU

-RRB-

a

local

memory

and

a

memory

flow

controller

An

overview

of

Cell

is

provided

in

Figure

Access

to

external

memory

is

handled

via

a

GB/s

XDR

memory

controller

The

cache

coherent

PowerPC

core

the

eight

SPEs

the

DRAM

controller

and

I/O

controllers

are

all

connected

via

data

rings

collectively

known

as

the

EIB

The

ring

interface

within

each

unit

allows

bytes/cycle

to

be

read

or

written

Simultaneous

transfers

on

the

same

ring

are

possible

All

transfers

are

orchestrated

by

the

PowerPC

core

Each

SPE

includes

four

single

precision

-LRB-

SP

-RRB-

pipelined

FMA

datapaths

and

one

double

precision

-LRB-

DP

-RRB-

half-pumped

-LRB-

the

double

precision

operations

within

a

SIMD

operation

must

be

serialized

-RRB-

pipelined

FMA

datapath

with

cycles

of

overhead

for

data

movement

-LSB-

-RSB-

Cell

has

a

cycle

in-order

execution

pipeline

and

forwarding

network

-LSB-

-RSB-

IBM

appears

to

have

solved

the

problem

of

inserting

a

-LRB-

-RRB-

cycle

DP

pipeline

into

a

stage

in-order

machine

by

choosing

the

minimum

effort/performance/power

solution

of

simply

stalling

for

cycles

after

issuing

a

DP

instruction

The

SPE

's

DP

throughput

-LSB-

-RSB-

of

one

DP

instruction

every

-LRB-

issue

stall

-RRB-

cycles

coincides

perfectly

with

this

reasoning

Thus

for

computationally

intense

algorithms

like

dense

matrix

multiply

-LRB-

GEMM

-RRB-

we

expect

SP

implementations

to

run

near

peak

whereas

DP

versions

would

drop

to

approximately

one

fourteenth

the

peak

SP

flop

rate

-LSB-

-RSB-

Similarly

for

bandwidth

intensive

applications

such

as

sparse

matrix

vector

multiplication

-LRB-

SpMV

-RRB-

we

expect

SP

versions

to

be

between

x

and

as

fast

as

DP

depending

on

density

and

uniformity

Unlike

a

typical

coprocessor

each

SPE

has

its

own

local

memory

from

which

it

fetches

code

and

reads

and

writes

data

All

loads

and

stores

issued

from

the

SPE

can

only

access

the

SPE

's

local

memory

The

Cell

processor

depends

on

explicit

DMA

operations

to

move

data

from

main

memory

to

the

local

store

of

the

SPE

The

limited

scope

of

loads

and

stores

allows

one

to

view

the

SPE

as

having

a

two-level

register

file

The

first

level

is

a

x

single

cycle

register

file

where

the

second

is

a

x

six

cycle

register

file

Data

must

be

moved

into

the

first

level

before

it

can

be

operated

on

by

instructions

Dedicated

DMA

engines

allow

multiple

concurrent

DMA

loads

to

run

concurrently

with

the

SIMD

execution

unit

thereby

mitigating

memory

latency

overhead

via

double-buffered

DMA

loads

and

stores

The

selectable

length

DMA

operations

supported

by

the

SPE

are

much

like

a

traditional

unit

stride

vector

load

We

exploit

these

similarities

to

existing

HPC

platforms

to

select

programming

models

that

are

both

familiar

and

tractable

for

scientific

application

developers

The

Cell

architecture

poses

several

challenges

to

programming

an

explicitly

controlled

memory

hierarchy

explicit

parallelism

between

the

SPEs

and

the

PowerPC

and

a

quadword

based

ISA

Our

goal

is

to

select

the

programming

paradigm

that

offers

the

simplest

possible

expression

of

an

algorithm

while

being

capable

of

fully

utilizing

the

hardware

resources

of

the

Cell

processor

The

memory

hierarchy

is

programmed

using

explicit

DMA

intrinsics

with

the

option

of

user

programmed

double

buffering

to

overlap

data

movement

with

computation

on

the

SPEs

Moving

from

a

hardware

managed

memory

hierarchy

to

one

controlled

explicitly

by

the

application

significantly

complicates

the

programming

model

and

pushes

it

towards

a

one

sided

communication

model

Unlike

MPI

the

intrinsics

are

very

low

level

and

map

to

half

a

dozen

instructions

This

allows

for

very

low

software

overhead

and

good

performance

but

requires

the

user

to

be

capable

and

either

ensure

correct

usage

or

provide

an

interface

or

abstraction

For

programming

the

parallelism

on

Cell

we

considered

three

possible

programming

models

task

parallelism

with

independent

tasks

scheduled

on

each

SPE

pipelined

parallelism

where

large

data

blocks

are

passed

from

one

SPE

to

the

next

and

data

parallelism

where

the

processors

perform

identical

computations

on

distinct

data

For

simplicity

we

do

not

consider

parallelism

between

the

PowerPC

and

the

SPEs

so

we

can

treat

this

as

a

homogeneous

parallel

machine

Data

pipelining

may

be

suitable

for

certain

classes

of

algorithms

and

will

be

the

focus

of

future

investigation

We

adopt

the

data-parallel

programming

model

which

is

a

good

match

to

many

scientific

applications

and

offers

the

simplest

and

most

direct

method

of

decomposing

the

problem

Data-parallel

programming

is

quite

similar

to

loop-level

parallelization

afforded

by

OpenMP

or

the

vector-like

multistreaming

on

the

Cray

and

the

Hitachi

The

focus

of

this

paper

is

Cell

architecture

and

performance

we

do

not

explore

the

efficacy

of

the

IBM

SPE

XLC

compiler

Thus

we

heavily

rely

on

SIMD

intrinsics

and

do

not

investigate

if

appropriate

SIMD

instructions

are

gener-ated

by

the

compiler

Although

the

produced

Cell

code

may

appear

verbose

due

to

the

use

of

intrinsics

instead

of

C

operators

it

delivers

readily

understandable

performance

Our

first

Cell

implementation

SpMV

required

about

a

month

of

learning

the

programming

model

the

architecture

the

compiler

the

tools

and

deciding

on

a

final

algorithmic

strategy

The

final

implementation

required

about

lines

of

code

The

next

code

development

examined

two

flavors

of

double

precision

stencil-based

algorithms

These

implementations

required

one

week

of

work

and

are

each

about

lines

with

an

additional

lines

of

common

code

The

programming

overhead

of

these

kernels

on

Cell

required

significantly

more

effort

than

the

scalar

version

's

lines

due

mainly

to

loop

unrolling

and

intrinsics

use

Although

the

stencils

are

a

simpler

kernel

the

SpMV

learning

experience

accelerated

the

coding

process

Having

become

experienced

Cell

programmers

the

single

precision

time

skewed

stencil

although

virtually

a

complete

rewrite

from

the

double

precision

single

step

version

required

only

a

single

day

to

code

debug

benchmark

and

attain

spectacular

results

of

over

Gflop/s

This

implementation

consists

of

about

lines

due

once

again

to

unrolling

and

the

heavy

use

of

intrinsics

The

simplicity

of

the

SPEs

and

the

deterministic

behavior

of

the

explicitly

controlled

memory

hierarchy

make

Cell

amenable

to

performance

prediction

using

a

simple

analytic

model

Using

this

approach

one

can

easily

explore

multiple

variations

of

an

algorithm

without

the

effort

of

programming

each

variation

and

running

on

either

a

fully

cycle-accurate

simulator

or

hardware

With

the

newly

released

cycle

accurate

simulator

-LRB-

Mambo

-RRB-

we

have

succesfully

validated

our

performance

model

for

SGEMM

SpMV

and

Stencil

Computations

as

will

be

shown

in

the

subsequent

sections

Our

modeling

approach

is

broken

into

two

steps

commensurate

with

the

two

phase

double

buffered

computational

model

The

kernels

were

first

segmented

into

code-snippets

that

operate

only

on

data

present

in

the

local

store

of

the

SPE

We

sketched

the

code

snippets

in

SPE

assembly

and

performed

static

timing

analysis

The

latency

of

each

operation

issue

width

limitations

and

the

operand

alignment

requirements

of

the

SIMD/quadword

SPE

execution

pipeline

determined

the

number

of

cycles

required

The

in-order

nature

and

fixed

local

store

memory

latency

of

the

SPEs

makes

the

analysis

deterministic

and

thus

more

tractable

than

on

cache-based

out-of-order

microprocessors

In

the

second

step

we

construct

a

model

that

tabulates

the

time

required

for

DMA

loads

and

stores

of

the

operands

required

by

the

code

snippets

The

model

accurately

reflects

the

constraints

imposed

by

resource

conflicts

in

the

memory

subsystem

For

instance

concurrent

DMAs

issued

by

multiple

SPEs

must

be

serialized

as

there

is

only

a

single

DRAM

controller

The

model

also

presumes

a

conservative

fixed

DMA

initiation

latency

of

cycles

The

model

computes

the

total

time

by

adding

all

the

Cell

SPE

Chip

-LRB-

MSP

-RRB-

SIMD

Multi-Multi

Super

VLIW

Architecture

core

chip

scalar

SIMD

Vector

Clock

-LRB-

GHz

-RRB-

DRAM

-LRB-

GB/s

-RRB-

SP

Gflop/s

DP

Gflop/s

Local

Store

MB

Cache

KB

MB

MB

Cache

MB

Power

-LRB-

W

-RRB-

Year

Table

Architectural

overview

of

STI

Cell

Cray

MSP

AMD

Opteron

and

Intel

Es-timated

total

Cell

power

and

peak

Gflop/s

are

based

on

the

active

SPEs/idle

PowerPC

programming

model

iteration

-LRB-

outer

loop

-RRB-

times

which

are

themselves

computed

by

taking

the

maximum

of

the

snippet

and

DMA

transfer

times

In

some

cases

the

per-iteration

times

are

constant

across

iterations

but

in

others

it

varies

between

iterations

and

is

input-dependent

For

example

in

a

sparse

matrix

the

memory

access

pattern

depends

on

the

nonzero

structure

of

the

matrix

which

varies

across

iterations

Some

algorithms

may

also

require

separate

stages

which

have

different

execution

times

e.g.

the

FFT

has

stages

for

loading

data

loading

constants

local

computation

transpose

local

computation

bit

reversal

and

storing

the

results

For

simplicity

we

chose

to

model

a

GHz

SPE

version

of

Cell

with

GB/s

of

memory

bandwidth

This

version

of

Cell

is

likely

to

be

used

in

the

first

release

of

the

Sony

-LSB-

-RSB-

The

lower

frequency

had

the

simplifying

benefit

that

both

the

EIB

and

DRAM

controller

could

deliver

two

SP

words

per

cycle

The

maximum

flop

rate

of

such

a

machine

would

be

Gflop/s

with

a

computational

intensity

of

FLOPs/word

For

comparison

we

ran

these

kernels

on

actual

hardware

of

several

leading

processor

designs

the

vector

Cray

MSP

superscalar

AMD

Opteron

and

VLIW

Intel

The

key

architectural

characteristics

are

detailed

in

Table

Cell

Architectural

Exploration

The

Double

Precision

-LRB-

DP

-RRB-

pipeline

in

Cell

is

obviously

an

afterthought

as

video

games

have

limited

need

for

DP

arithmetic

Certainly

a

redesigned

pipeline

would

rectify

the

performance

limitations

but

would

do

so

at

a

cost

of

additional

design

complexity

and

power

consumption

We

offer

a

more

modest

alternative

that

can

reuse

most

of

the

existing

circuitry

Based

on

our

experience

designing

the

VI-RAM

vector

processor-in-memory

chip

-LSB-

-RSB-

we

believe

these

Cell

design

modifications

are

considerably

less

complex

than

a

redesigned

pipeline

consume

very

little

additional

surface

area

on

the

chip

but

show

significant

DP

performance

improvements

for

scientific

kernels

In

order

to

explore

the

limitations

of

Cell

's

DP

issue

bandwidth

we

propose

an

alternate

design

with

a

longer

forwarding

network

to

eliminate

the

all

but

one

of

the

stall

cycles

recall

the

factors

that

limit

DP

throughput

as

described

in

Section

In

this

hypothetical

implementation

called

Cell

each

SPE

would

still

have

the

single

DP

datapath

but

would

be

able

to

dispatch

one

DP

SIMD

instruction

every

other

cycle

instead

of

one

every

cycles

The

Cell

design

would

not

stall

issuing

other

instructions

and

would

achieve

x

the

DP

throughput

of

the

Cell

-LRB-

Gflop/s

-RRB-

by

fully

utilizing

the

existing

DP

datapath

however

it

would

maintain

the

same

SP

throughput

frequency

bandwidth

and

power

as

the

Cell

We

begin

by

examining

the

performance

of

dense

matrix-matrix

multiplication

or

GEMM

This

kernel

is

character-ized

by

high

computational

intensity

and

regular

memory

access

patterns

making

it

an

extremely

well

suited

for

the

Cell

architecture

We

explored

two

storage

formats

column

major

and

block

data

layout

-LSB-

-RSB-

-LRB-

BDL

-RRB-

BDL

is

a

two-stage

addressing

scheme

-LRB-

block

row/column

element

sub

row/column

-RRB-

Algorithm

Considerations

For

GEMM

we

adopt

what

is

in

essence

an

outer

loop

parallelization

approach

Each

matrix

is

broken

into

x

n

element

tiles

designed

to

fit

into

the

memory

available

on

the

Cell

chip

which

are

in

turn

split

into

eight

n

x

n

element

tiles

that

can

fit

into

the

SPE

local

stores

For

the

column

layout

the

matrix

will

be

accessed

via

a

number

of

short

DMAs

equal

to

the

dimension

of

the

tile

e.g.

DMAs

of

length

BDL

on

the

other

hand

will

require

a

single

long

DMA

of

length

Since

the

local

store

is

only

and

must

contain

both

the

program

and

stack

program

data

in

the

local

store

is

limited

to

about

words

The

tiles

when

double

buffered

require

words

of

local

store

-LRB-

one

from

each

matrix

-RRB-

thus

making

the

maximum

square

tiles

in

SP.

Additionally

in

column

layout

there

is

added

pressure

on

the

maximum

tile

size

for

large

matrices

as

each

column

within

a

tile

will

be

on

a

different

page

resulting

in

TLB

misses

The

minimum

size

of

a

tile

is

determined

by

the

FLOPs

to

word

ratio

of

the

processor

In

the

middle

there

is

a

tile-size

sweet

spot

that

delivers

peak

performance

The

loop

order

was

therefore

chosen

to

minimize

the

average

number

of

pages

touched

per

phase

for

a

column

major

storage

format

The

BDL

approach

as

TLB

misses

are

of

little

concern

allows

us

to

structure

the

loop

order

to

minimize

memory

bandwidth

requirements

A

possible

alternate

approach

is

to

adapt

Cannon

's

algorithm

-LSB-

-RSB-

for

parallel

machines

Although

this

strategy

could

reduce

the

DRAM

bandwidth

requirements

by

transferring

blocks

via

the

EIB

for

a

column

major

layout

it

could

significantly

increase

the

number

of

pages

touched

This

will

be

the

subject

of

future

work

Note

that

for

small

matrix

sizes

it

is

most

likely

advantageous

to

choose

an

algorithm

that

minimizes

the

number

of

DMAs

One

such

solution

would

be

to

broadcast

a

copy

of

the

first

matrix

to

all

SPEs

Single

Precision

GEMM

Results

The

Cell

performance

of

GEMM

based

on

our

performance

model

-LRB-

referred

to

as

Cell

pm

-RRB-

for

large

matrices

is

presented

in

Table

SGEMM

simulation

data

show

that

blocks

do

not

achieve

sufficient

computational

intensity

to

fully

utilize

the

processor

The

choice

of

loop

order

Cell

pm

Cell

pm

DP

-LRB-

Gflop/s

-RRB-

SP

-LRB-

Gflop/s

-RRB-

Table

GEMM

performance

-LRB-

in

Gflop/s

-RRB-

for

large

square

matrices

on

Cell

Opteron

and

Only

the

best

performing

numbers

are

shown

Cell

data

based

on

our

performance

model

is

referred

to

as

Cell

pm

and

the

resulting

increase

in

memory

traffic

prevents

column

major

blocks

from

achieving

a

large

fraction

of

peak

-LRB-

over

-RRB-

for

large

matrices

Only

block

sizes

provide

enough

computational

intensity

to

overcome

the

additional

block

loads

and

stores

and

thus

achieving

near-peak

performance

over

For

BDL

however

blocks

effectively

achieve

peak

performance

Whereas

we

assume

a

cycle

DMA

startup

latency

in

our

simulations

if

the

DMA

latency

were

only

cycles

then

the

column

major

performance

would

reach

parity

with

BDL

At

GHz

each

SPE

requires

about

-LSB-

-RSB-

Thus

with

a

nearly

idle

PPC

and

Cell

pm

achieves

over

Gflop/s

for

approximately

of

power

nearly

Gflop/s/Watt

Clearly

for

well-suited

applications

Cell

is

extremely

power

efficient

Double

Precision

GEMM

Results

A

similar

set

of

strategies

and

simulations

were

performed

for

DGEMM

Although

the

time

to

load

a

DP

block

is

twice

that

of

the

SP

version

the

time

required

to

compute

on

a

DP

block

is

about

as

long

as

the

SP

counterpart

-LRB-

due

to

the

limitations

of

the

DP

issue

logic

-RRB-

Thus

it

is

far

easier

for

DP

to

reach

its

peak

performance

a

mere

Gflop/s

However

when

using

our

proposed

Cell

hardware

variant

DGEMM

performance

jumps

to

an

impressive

Gflop/s

Performance

Comparison

Table

shows

a

performance

comparison

of

GEMM

between

Cell

pm

and

the

set

of

modern

processors

evaluated

in

our

study

Note

the

impressive

performance

characteristics

of

the

Cell

processors

achieving

and

speed

up

for

SGEMM

compared

with

the

Opteron

and

respectively

For

DGEMM

the

default

Cell

processor

is

x

and

x

faster

than

the

and

Opteron

In

terms

of

power

the

Cell

performance

is

even

more

impressive

achieving

over

the

efficiency

of

the

for

SGEMM

Our

Cell

pm

exploration

architecture

is

capable

for

large

tiles

of

fully

exploiting

the

DP

pipeline

and

achieving

over

Gflop/s

In

DP

the

Cell

architecture

would

be

nearly

times

faster

than

the

and

nearly

times

more

power

efficient

Additionally

traditional

micros

-LRB-

Opteron

etc

-RRB-

in

multi-core

configurations

would

require

either

enormous

power

saving

innovations

or

dramatic

reductions

in

performance

and

thus

would

show

even

poorer

performance/power

compared

with

the

Cell

technology

Com-pared

to

the

Cell

would

be

times

as

fast

and

times

more

power

efficient

The

decoupling

of

main

memory

data

access

from

the

computational

kernel

guarantees

constant

memory

access

latency

since

there

will

be

no

cache

misses

and

all

TLB

accesses

are

resolved

in

the

communication

phase

Matrix

multiplication

is

perhaps

the

best

benchmark

to

demonstrate

Cell

's

computational

capabilities

as

it

achieves

high

performance

by

buffering

large

blocks

on

chip

before

computing

on

them

Model

Validation

IBM

recently

released

their

in-house

performance

evaluation

of

their

prototype

hardware

-LSB-

-RSB-

On

SGEMM

they

achieve

about

Gflop/s

which

is

within

of

our

pred-icated

performance

At

first

glance

SpMV

would

seem

to

be

a

poor

application

choice

for

the

Cell

since

the

SPEs

have

neither

caches

nor

word-granularity

gather/scatter

support

Furthermore

SpMV

has

a

relatively

low

O

-LRB-

-RRB-

computational

intensity

However

these

considerations

are

perhaps

less

important

than

the

Cell

's

low

functional

unit

and

local

store

latency

-LRB-

-RRB-

the

task

parallelism

afforded

by

the

SPEs

the

eight

independent

load

store

units

and

the

ability

to

stream

nonzeros

via

DMAs

Algorithmic

Considerations

Two

storage

formats

are

presented

in

this

paper

Compressed

Sparse

Row

-LRB-

CSR

-RRB-

and

Blocked

Compressed

Sparse

Row

-LRB-

BCSR

-RRB-

Only

square

BCSR

was

explored

and

only

BCSR

numbers

will

be

presented

here

Future

Cell

SpMV

work

will

examine

the

entire

BCSR

space

Because

of

the

quadword

nature

of

the

SPEs

all

rows

within

a

CSR

tile

are

padded

to

a

multiple

of

This

greatly

simplifies

the

programming

model

at

the

expense

of

increasing

memory

traffic

Note

that

this

is

very

different

than

BCSR

To

perform

a

stanza

gather

operation

the

Cell

utilizes

the

MFC

get

list

command

where

a

list

of

addresses/lengths

is

created

in

local

store

The

MFC

then

gathers

these

stanzas

from

the

global

store

and

packs

them

into

the

local

store

It

is

possible

to

make

every

stanza

a

single

quadword

however

without

an

accurate

performance

model

of

the

MFC

get

list

command

one

must

resort

to

tiling

to

provide

a

reasonable

estimate

for

performance

For

simplicity

all

benchmarks

were

run

using

square

tiles

The

data

structure

required

to

store

the

entire

matrix

is

a

array

of

tiles

where

each

block

stores

its

nonzeros

and

row

pointers

as

if

it

were

an

entire

matrix

We

chose

not

to

buffer

the

source

and

destination

vector

tiles

as

this

would

result

in

a

smaller

block

size

These

tradeoffs

will

be

examined

in

future

work

Collectively

the

blocks

are

chosen

to

be

no

larger

than

words

in

SP

-LRB-

half

that

in

DP

-RRB-

The

inner

loop

of

CSR

SpMV

either

requires

significant

software

pipelining

hefty

loop

unrolling

or

an

approach

al-gorithmically

analogous

to

a

segmented

scan

-LSB-

-RSB-

As

there

are

no

conditional

stores

in

the

SPE

assembly

language

we

chose

to

partially

implement

a

segmented

scan

where

the

gather

operations

are

decoupled

from

the

dot

products

This

decoupled

gather

operation

can

be

unrolled

and

software

pipelined

thereby

completing

in

close

to

three

cycles

per

element

-LRB-

the

ISA

is

not

particularly

gather

friendly

-RRB-

It

is

important

to

note

that

since

the

local

store

is

not

a

write

back

cache

it

is

possible

to

overwrite

its

contents

without

fear

of

consuming

DRAM

bandwidth

or

corrupting

the

actual

arrays

As

the

nonzeros

are

stored

contiguously

in

arrays

it

is

Name

N

NNZ

Comments

Vavasis

M

PDE

Problem

FEM

Fluid

Mechanics

Problem

Memory

MotorolaMemory

Circuit

CFD

Navier-Stokes

viscous

flow

FEM

Crystal

FEM

stiffness

matrix

Tube

M

pressure

Tube

Portfolio

Financial

Portfolio

NASA

PWT

NASA

Matrix

Vibroacoustic

Flexible

box

structure

Linear

Prog

AA

T

pt

M

pt

stencil

Table

Suite

of

matrices

used

to

evaluate

SpMV

performance

Matrix

numbers

as

defined

in

the

SPARSITY

suite

are

shown

in

the

first

column

straightforward

to

stream

them

in

via

DMA

Here

unlike

the

source

and

destination

vectors

it

is

essential

to

double

buffer

in

order

to

maximize

the

SPEs

computational

throughput

Using

buffers

of

for

SP

allows

for

values

and

indices

for

CSR

and

tiles

for

BCSR

Note

that

for

each

phase

loading

nonzeros

and

indices

there

is

the

omnipresent

cycle

DMA

latency

overhead

in

addition

to

the

startup

and

finalize

penalties

-LRB-

as

in

traditional

pipelining

-RRB-

To

partition

the

work

among

the

SPEs

we

implemented

a

cooperative

blocking

model

By

forcing

all

SPEs

to

work

on

the

same

block

it

is

possible

to

broadcast

the

blocked

source

vector

and

row

pointers

to

minimize

memory

traffic

One

approach

referred

to

as

PrivateY

was

to

divide

work

among

SPEs

within

a

block

by

distributing

the

nonzeros

as

evenly

as

possible

This

strategy

necessitates

that

each

SPE

contains

a

private

copy

of

the

destination

vector

and

requires

an

inter-SPE

reduction

at

the

end

of

each

blocked

row

The

alternate

method

referred

to

as

PartitionedY

partitions

the

destination

vector

evenly

among

the

SPEs

However

there

is

no

longer

any

guarantee

that

the

SPEs

computations

will

remain

balanced

causing

the

execution

time

of

the

entire

tile

to

be

limited

by

the

most

heavily

loaded

SPE

Thus

for

load

balanced

blocks

the

PartitionedY

approach

is

generally

advantageous

however

for

matrices

exhibiting

irregular

-LRB-

uneven

-RRB-

nonzero

patterns

we

expect

higher

performance

using

PrivateY

Note

that

there

is

a

potential

performance

benefit

by

writing

a

kernel

specifically

optimized

for

symmetric

matrices

For

these

types

of

matrices

the

number

of

operations

can

effectively

double

relative

to

the

memory

traffic

However

the

algorithm

must

block

two

tiles

at

a

time

thus

the

symmetric

matrix

kernel

divides

memory

allocated

for

blocking

the

vector

evenly

among

the

two

submatrices

and

performs

a

dot

product

and

SAXPY

for

each

row

in

the

lower

triangle

Evaluation

Matrices

In

order

to

effectively

evaluate

SpMV

performance

we

examine

a

synthetic

stencil

matrix

as

well

as

ten

real

matrices

used

in

numerical

calculations

from

the

BeBop

SPARSITY

suite

-LSB-

-RSB-

-LRB-

four

nonsymmetric

and

six

symmetric

-RRB-

Table

presents

an

overview

of

the

evaluated

matrices

Single

Precision

SpMV

Results

Single

and

double

precision

tuned

SpMV

results

for

the

SPARSITY

matrices

are

show

in

Tables

and

Surpris-ingly

given

Cell

's

inherent

SpMV

limitations

the

SPARSITY

nonsymmetric

matrices

average

over

Gflop/s

while

the

symmetric

matrices

average

nearly

Gflop/s

Unfortunately

many

of

these

matrices

are

so

small

that

they

utilize

only

a

fraction

of

the

default

tile

size

Unlike

the

synthetic

matrices

the

real

matrices

which

contain

dense

sub-blocks

can

exploit

BCSR

without

unnecessarily

wasting

memory

bandwidth

on

zeros

As

memory

traffic

is

key

storing

BCSR

blocks

in

a

compressed

format

-LRB-

the

zeros

are

neither

stored

nor

loaded

-RRB-

would

allow

for

significantly

higher

performance

if

there

is

sufficient

support

within

the

ISA

to

either

decompress

these

blocks

on

the

fly

or

compute

on

compressed

blocks

This

is

an

area

of

future

research

Overall

results

show

that

the

PrivateY

approach

is

generally

a

superior

partitioning

strategy

compared

with

PartitionedY

In

most

cases

the

matrices

are

sufficiently

unbalanced

that

the

uniform

partitioning

of

the

nonzeros

coupled

with

a

reduction

requires

less

time

than

the

performing

a

load

imbalanced

calculation

When

using

the

PartionedY

approach

the

symmetric

kernel

is

extremely

unbalanced

for

blocks

along

the

diagonal

Thus

for

matrices

approximately

the

size

of

a

single

block

the

imbalance

between

SPEs

can

severely

impair

the

performance

even

if

the

matrix

is

uniform

In

fact

symmetric

optimizations

show

only

about

performance

improvement

when

running

the

nonsymmetric

kernel

on

the

symmetric

matrices

Once

again

DMA

latency

plays

a

relatively

small

role

in

this

algorithm

In

fact

reducing

the

DMA

latency

by

a

factor

of

ten

results

in

only

a

increase

in

performance

This

is

actually

a

good

result

It

means

than

the

memory

bandwidth

is

highly

utilized

and

the

majority

of

bus

cycles

are

used

for

transferring

data

rather

than

stalls

On

the

whole

clock

frequency

also

plays

a

small

part

in

the

overall

performance

Solely

increasing

the

clock

frequency

by

a

factor

of

-LRB-

to

GHz

-RRB-

provides

only

a

increase

in

performance

on

the

SPARSITY

nonsymmetric

matrix

suite

Similarly

cutting

the

frequency

in

half

-LRB-

to

GHz

-RRB-

results

in

only

a

decrease

in

performance

Simply

put

for

the

common

case

more

time

is

used

in

transferring

nonzeros

and

the

vectors

rather

than

computing

on

them

Double

Precision

SpMV

Results

Results

from

our

performance

estimator

show

that

single

precision

SPMV

is

almost

twice

as

fast

as

double

precision

even

though

the

nonzero

memory

traffic

only

increases

by

This

discrepancy

is

due

to

the

reduction

in

the

number

of

values

contained

in

a

tile

where

twice

as

many

blocked

rows

are

present

For

example

when

using

SP

tiles

on

a

matrix

the

source

vector

must

be

loaded

times

However

in

DP

the

tiles

are

only

causing

the

MB

source

vector

to

be

loaded

times

and

thus

resulting

in

a

much

higher

volume

of

memory

traffic

Future

work

will

investigate

caching

mega

blocks

across

SPEs

to

reduce

total

memory

traffic

Performance

Comparison

Table

compares

Cell

's

estimated

performance

-LRB-

the

best

partitioning

and

blocking

combination

-RRB-

for

SpMV

with

SPARSITY

nonsymmetric

matrix

suite

Double

Precision

-LRB-

Gflop/s

-RRB-

Single

Precision

-LRB-

Gflop/s

-RRB-

Matrix

Cell

F

SS

Cell

pm

Cell

pm

Cell

pm

Vavasis

FEM

Mem

CFD

Average

SPARSITY

symmetric

matrix

suite

Double

Precision

-LRB-

Gflop/s

-RRB-

Single

Precision

-LRB-

Gflop/s

-RRB-

Matrix

Cell

F

SS

Cell

pm

Cell

pm

Cell

pm

FEM

Tube

Portfolio

NASA

Vibro

LP

Average

Synthetic

Matrices

Double

Precision

-LRB-

Gflop/s

-RRB-

Single

Precision

-LRB-

Gflop/s

-RRB-

Matrix

Cell

F

SS

Cell

pm

Cell

pm

Cell

pm

pt

Stencil

Table

SpMV

performance

in

single

and

double

precision

on

the

SPARSITY

-LRB-

top

-RRB-

nonsymmetric

and

-LRB-

bottom

-RRB-

symmetric

matrix

suites

Note

Cell

F

SS

represents

the

actual

implementation

and

runs

on

the

cycle

accurate

full

system

simulator

sults

from

the

and

Opteron

using

SPARSITY

a

highly

tuned

sparse

matrix

numerical

library

on

nonsymmetric

-LRB-

top

-RRB-

and

symmetric

matrix

suites

results

where

gathered

using

a

high-performance

SpMV

implementation

-LSB-

-RSB-

Considering

that

the

and

Opteron

each

have

a

GB/s

bus

compared

to

the

Cell

's

GB/s

DRAM

bandwidth

one

may

expect

that

a

memory

bound

application

such

as

SpMV

would

perform

only

four

times

better

on

the

Cell

Nonetheless

on

average

Cell

pm

is

more

than

faster

in

DP

and

faster

in

SP.

This

is

because

in

order

to

achieve

maximum

performance

the

must

rely

on

the

BCSR

storage

format

and

thus

waste

memory

bandwidth

loading

unnecessary

zeros

However

the

Cell

's

high

FLOP

to

byte

ratio

ensures

that

the

regularity

of

BCSR

is

unnecessary

allowing

it

to

avoid

loading

many

of

the

superfluous

zeros

For

example

in

matrix

Cell

uses

more

than

of

its

bandwidth

loading

just

the

DP

nonzero

values

while

the

utilizes

only

of

its

bandwidth

The

rest

of

's

bandwidth

is

used

for

zeros

and

meta

data

It

should

be

noted

that

where

simulations

on

Cell

involve

a

cold

start

to

the

local

store

the

's

have

the

additional

advantage

of

a

warm

cache

Cell

's

use

of

on-chip

memory

as

a

buffer

is

advantageous

in

both

power

and

area

compared

with

a

traditional

cache

In

fact

Cell

is

times

more

power

efficient

than

the

and

times

more

efficient

than

the

Opteron

for

SpMV

For

a

memory

bound

application

such

as

this

multicore

commodity

processors

will

see

little

performance

improvement

unless

they

also

scale

memory

bandwidth

Comparing

results

with

an

MSP

is

far

more

difficult

For

unsymmetric

matrices

the

Cell

pm

performance

on

average

is

twice

that

of

the

For

symmetric

matrices

Cell

pm

performs

somewhere

between

half

and

triple

the

performance

of

the

but

on

average

is

faster

The

fact

that

the

consumes

about

three

times

the

power

of

Cell

guarantees

Cell

in

double

precision

is

at

least

as

power

efficient

as

the

Model

Validation

Some

might

claim

that

matrix-matrix

multiplication

performance

can

be

easily

predictable

Most

however

would

agree

that

SpMV

is

very

difficult

to

predict

As

seen

in

Table

we

tested

our

implementation

of

the

DP

SpMV

kernel

on

the

cycle

accurate

IBM

full

system

simulator

referred

to

as

Cell

F

SS

The

actual

implementation

makes

dynamic

blocking

and

partitioning

decisions

at

run

time

based

on

the

lessons

learned

while

exploring

optimization

strategies

for

the

performance

model

however

the

current

version

but

does

not

include

the

BCSR

approach

and

only

pads

rows

to

the

nearest

even

number

The

cycle

accurate

simulations

with

a

superior

implementation

proved

to

be

about

faster

than

the

initial

performance

estimate

and

averages

impressive

results

of

more

than

Gflop/s

for

nonsymmetric

matrices

The

discrepancy

disappears

when

static

partitioning

and

blocking

strategies

used

We

can

clearly

see

how

the

actual

implemen-tation

's

run

time

search

for

structure

boosted

performance

of

the

heat

equation

from

about

Gflop/s

to

Gflop/s

achieving

a

speedup

over

the

Cell

F

SS

for

double

precision

nonsymmetric

matrices

is

more

than

times

faster

than

the

and

times

more

power

efficient

These

results

confirm

our

performance

model

's

predictive

X

next

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

dt

dx

-LRB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

-RRB-

dt

dy

-LRB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

-RRB-

dt

dz

-LRB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

-RRB-

X

-LSB-

i

j

k

t

-RSB-

X

-LSB-

i

j

k

t

-RSB-

Figure

Stencil

kernels

used

in

evaluation

Top

Chombo

heattut

equation

requires

only

the

previous

time

step

Bottom

Cactus

WaveToy

equation

requires

both

two

previous

time

steps

abilities

on

complex

kernels

and

clearly

demonstrate

Cell

's

performance

superiority

when

compared

with

leading

microarchitectural

approaches

Stencil-based

computations

on

regular

grids

are

at

the

core

of

a

wide

range

of

important

scientific

applications

In

these

applications

each

point

in

a

multidimensional

grid

is

updated

with

contributions

from

a

subset

of

its

neighbors

The

numerical

operations

are

then

used

to

build

solvers

that

range

from

simple

Jacobi

iterations

to

complex

multigrid

and

block

structured

adaptive

methods

In

this

work

we

examine

two

flavors

of

stencil

computations

derived

from

the

numerical

kernels

of

the

Chombo

-LSB-

-RSB-

and

Cactus

-LSB-

-RSB-

toolkits

Chombo

is

a

framework

for

computing

solutions

of

partial

differential

equations

-LRB-

PDEs

-RRB-

using

finite

difference

methods

on

adaptively

refined

meshes

Here

we

examine

a

stencil

computation

based

on

Chombo

's

demo

application

heattut

which

solves

a

simple

heat

equation

without

adaptivity

Cactus

is

modular

open

source

framework

for

computational

science

successfully

used

in

many

areas

of

astrophysics

Our

work

examines

the

stencil

kernel

of

the

Cactus

demo

WaveToy

which

solves

a

hyperbolic

PDE

by

finite

differencing

The

heattut

and

WaveToy

equations

are

shown

in

Figure

Notice

that

both

kernels

solve

point

stencils

in

for

each

point

However

the

heattut

equation

only

utilizes

values

from

the

previous

time

step

while

WaveToy

requires

values

from

the

two

previous

timesteps

Additionally

WaveToy

has

a

higher

computational

intensity

and

can

more

readily

exploit

the

FMA

pipeline

Algorithmic

Considerations

The

algorithm

used

on

Cell

is

virtually

identical

to

that

used

on

traditional

architectures

except

that

the

ISA

forces

main

memory

loads

and

stores

to

be

explicit

rather

than

caused

by

cache

misses

and

evictions

The

basic

algorithmic

approach

to

update

the

cubic

data

array

is

to

sweep

across

the

domain

updating

one

plane

at

a

time

Since

a

stencil

requires

both

the

next

and

previous

plane

a

minimum

of

planes

must

be

present

in

the

local

stores

-LRB-

t

-RRB-

Z

Z

Z

Z

Time

t

Time

t

Z

Z

Z

Time

t

Time

t

Z

Time

t

Figure

Flow

Diagram

for

Heat

equation

flow

diagram

Left

Queues

implemented

within

each

SPE

perform

only

one

time

step

Right

Time

skewing

version

requires

an

additional

circular

queue

to

hold

intermediate

results

-LRB-

z

t

-RRB-

-LRB-

z

t

-RRB-

and

-LRB-

z

t

-RRB-

Additionally

bus

utilization

can

be

maximized

by

double

buffering

the

previous

output

plane

-LRB-

t

-RRB-

with

the

next

input

plane

-LRB-

z

t

-RRB-

In

order

to

parallelize

across

SPEs

each

plane

of

the

domain

is

partitioned

into

eight

overlapping

blocks

Due

to

the

finite

size

of

the

local

store

memory

a

straightforward

stencil

calculation

is

limited

to

planes

of

elements

plus

ghost

regions

Thus

each

SPE

updates

the

core

points

from

a

slab

-LRB-

as

slabs

also

contain

ghost

regions

-RRB-

To

improve

performance

of

stencil

computations

on

cache-based

architectures

previous

research

has

shown

multiple

time

steps

can

be

combined

to

increase

performance

-LSB-

-RSB-

This

concept

of

time

skewing

can

also

be

effectively

leveraged

in

our

Cell

implementation

By

keeping

multiple

planes

from

multiple

time

steps

in

the

SPE

simul-taneously

it

is

possible

to

double

or

triple

the

number

of

stencils

performed

with

almost

no

increase

in

memory

traffic

thus

increasing

computational

intensity

and

improving

overall

performance

Figure

details

a

flow

diagram

for

the

heat

equation

showing

both

the

simple

and

time

skewed

implementations

Note

that

the

neighbor

communication

required

by

stencils

is

not

well

suited

for

the

aligned

quadword

load

requirements

of

the

SPE

ISA

i.e.

unaligned

loads

must

be

emu-lated

with

permute

instructions

In

fact

for

SP

stencils

with

extensive

unrolling

after

memory

bandwidth

the

permute

datapath

is

the

limiting

factor

in

performance

not

the

FPU

This

lack

of

support

for

unaligned

accesses

highlights

a

potential

bottleneck

of

the

Cell

architecture

however

we

can

partially

obviate

this

problem

for

the

stencil

kernel

via

data

padding

Stencil

Kernel

Results

The

performance

estimation

for

the

heattut

and

WaveToy

stencil

kernels

is

shown

in

Table

Results

show

that

as

the

number

of

time

steps

increases

a

corresponding

decrease

in

the

grid

size

is

required

due

to

the

limited

memory

footprint

of

the

local

store

In

SP

the

heat

equation

on

the

Cell

pm

is

effectively

computationally

bound

with

two

steps

of

time

skewing

resulting

in

over

Gflop/s

More

specifically

the

permute

unit

becomes

fully

utilized

as

discussed

Double

Precision

-LRB-

Gflop/s

-RRB-

Cell

F

SS

Cell

pm

Cell

pm

Cell

pm

Stencil

-LRB-

step

-RRB-

Heat

WaveToy

Single

Precision

-LRB-

Gflop/s

-RRB-

Cell

F

SS

Cell

pm

Cell

pm

Stencil

-LRB-

step

-RRB-

-LRB-

step

-RRB-

Heat

WaveToy

Table

Performance

for

the

Heat

equation

and

WaveToy

stencils

and

experiments

use

grids

The

Opteron

uses

a

Cell

uses

the

largest

grid

that

would

fit

within

the

local

stores

The

-LRB-

n

steps

-RRB-

versions

denote

a

time

skewed

version

where

n

time

steps

are

computed

in

Section

In

DP

however

the

heat

equation

is

truly

computationally

bound

for

only

a

single

time

step

achieving

Gflop/s

Analysis

also

shows

that

in

the

Cell

approach

the

heat

equation

is

memory

bound

when

using

a

single

time

step

attaining

Gflop/s

for

time

skewing

performance

of

Cell

DP

jumps

to

over

Gflops/s

We

believe

the

temporal

recurrence

in

the

CACTUS

WaveToy

example

will

allow

more

time

skewing

in

single

precision

at

the

expense

of

far

more

complicated

code

and

will

be

the

subject

of

future

investigation

Performance

Comparison

Table

presents

a

performance

comparison

of

the

stencil

computations

across

our

evaluated

set

of

leading

processors

Note

that

stencil

performance

has

been

optimized

for

the

cache-based

platforms

as

described

in

-LSB-

-RSB-

In

single

precision

for

this

memory

bound

computation

even

without

time

skewing

Cell

pm

achieves

x

and

speedup

compared

with

the

the

and

the

Opteron

respectively

Recall

that

the

Cell

has

only

four

times

the

memory

bandwidth

the

scalar

machines

and

the

bandwidth

of

the

indicating

that

Cells

potential

to

perform

this

class

of

computations

in

a

much

more

efficient

manner

is

due

to

the

advantages

of

software

controlled

memory

for

algorithms

exhibiting

predictable

memory

accesses

In

double

precision

with

th

the

floating

point

throughput

Cell

pm

achieves

a

and

speedup

compared

to

the

the

and

the

Opteron

for

the

heat

equation

a

truly

impressive

result

Additionally

unlike

the

Opteron

and

simple

time

skewing

has

the

potential

to

at

least

double

the

performance

in

either

SP

-LRB-

either

version

of

Cell

-RRB-

or

in

DP

on

the

Cell

variant

Finally

recall

that

in

Section

we

examined

Cell

SpMV

performance

using

stencil

matrices

We

can

now

compare

those

results

with

the

structured

grid

approach

presented

here

as

the

numerical

computations

are

equivalent

in

both

cases

Results

show

that

for

two

time

step

calculations

the

single

precision

structured

grid

approach

achieves

a

advantage

compared

with

the

sparse

matrix

method

This

impressive

speedup

is

attained

through

the

regularity

of

memory

accesses

reduction

of

memory

traffic

-LRB-

constants

are

encoded

in

the

equation

rather

than

the

matrix

-RRB-

the

ability

to

time

skew

-LRB-

increased

computational

intensity

-RRB-

and

that

stencils

on

a

structured

grid

dont

require

multiplications

by

like

a

sparse

matrix

would

For

double

precision

the

stencil

algorithm

advantage

is

diminished

to

approximately

due

mainly

to

the

lack

of

time

skewing

Model

Validation

As

with

SpMV

we

implemented

an

actual

double

precision

kernel

on

the

full

system

simulator

with

Cell

F

SS

results

shown

in

Table

At

first

we

were

surprised

that

measured

performance

fell

short

of

our

prediction

by

However

upon

closer

examination

it

was

discovered

that

the

actual

Cell

implementation

prohibits

dual

issuing

of

DP

instructions

with

loads

or

permutes

even

though

it

allows

SP

with

loads

or

permutes

to

be

dual

issued

Thus

for

kernels

with

streaming

behavior

it

is

realistic

to

assume

that

one

double

precision

SIMD

instruction

can

be

executed

every

cycles

instead

of

every

as

we

had

predicted

previously

This

discrepancy

results

in

a

architectural

performance

reduction

which

corresponding

very

well

to

the

difference

observed

in

Table

between

the

predicted

-LRB-

Cellpm

-RRB-

and

simulated

-LRB-

Cell

F

SS

-RRB-

DP

data

Nonetheless

the

actual

DP

Cell

F

SS

implementation

of

our

evaluated

stencil

kernel

is

about

faster

and

nearly

more

power

efficient

than

the

Opteron

We

also

developed

a

SP

version

of

the

heat

equation

that

allowed

four

time-skewed

stencil

steps

-LRB-

Our

original

performance

estimation

assumed

one

or

two

time

steps

-RRB-

Results

show

spectacular

SP

Cell

F

SS

performance

of

nearly

Gflop/s

more

than

faster

and

power

efficient

compared

with

the

Opteron

even

though

Cell

has

only

four

times

the

bandwidth

and

times

the

single

precision

throughput

The

FFT

presents

us

with

an

interesting

challenge

its

computational

intensity

is

much

less

than

matrix-matrix

multiplication

and

standard

algorithms

require

a

non-trivial

amount

of

data

movement

Extensive

work

has

been

performed

on

optimizing

this

kernel

for

both

vector

-LSB-

-RSB-

and

cache-based

-LSB-

-RSB-

machines

In

addition

implementations

for

varying

precisions

appear

in

many

embedded

devices

using

both

general

and

special

purpose

hardware

In

this

section

we

evaluate

the

implementation

of

a

standard

FFT

algorithm

on

the

Cell

processor

Methods

We

examine

both

the

FFT

cooperatively

executed

across

the

SPEs

and

a

FFT

whose

FFTs

are

each

run

on

a

single

SPE

In

all

cases

the

data

appears

in

a

single

array

of

complex

numbers

Internally

-LRB-

within

the

local

stores

-RRB-

the

data

is

unpacked

into

separate

arrays

and

a

table

lookup

is

used

for

the

roots

of

unity

so

that

no

runtime

computation

of

roots

is

required

As

such

our

results

include

the

time

needed

to

load

this

table

Additionally

all

results

are

presented

to

the

FFT

algorithm

and

returned

in

natural

order

-LRB-

i.e.

a

bit

reversal

was

required

to

unwind

the

permutation

process

in

all

cases

-RRB-

Note

that

these

requirements

have

the

potential

to

severely

impact

performance

For

simplicity

we

evaluated

a

naive

FFT

algorithm

-LRB-

no

double

buffering

and

with

barriers

around

computational

segments

-RRB-

for

the

single

FFT

The

data

blocks

are

dis-tributed

cyclically

to

SPEs

stages

of

local

work

are

performed

the

data

is

transposed

-LRB-

basically

the

reverse

of

the

cyclic

allocation

-RRB-

and

then

to

stages

of

local

computation

is

performed

-LRB-

depending

on

the

FFT

size

-RRB-

At

that

point

the

indices

of

the

data

on

chip

are

bit-reversed

to

unwind

the

permutation

process

and

the

naturally

ordered

result

copied

back

into

main

memory

Once

again

we

presume

a

large

DMA

initiation

overhead

of

cycles

However

a

Cell

implementation

where

the

DMA

initiation

overhead

is

smaller

would

allow

the

possibility

of

much

larger

FFT

calculations

-LRB-

including

out

of

core

FFTs

-RRB-

using

smaller

block

transfers

with

little

or

no

slowdown

using

double

buffering

to

hide

the

DMA

latency

Before

exploring

the

FFT

we

briefly

discuss

simultaneous

FFTs

For

sufficiently

small

FFTs

-LRB-

points

in

SP

-RRB-

it

is

possible

to

both

double

buffer

and

round

robin

allocate

a

large

number

of

independent

FFTs

to

the

SPEs

Although

there

is

lower

computational

intensity

the

sheer

parallelism

and

double

buffering

allow

for

extremely

high

performance

-LRB-

up

to

Gflop/s

-RRB-

Simultaneous

FFTs

form

the

core

of

the

FFT

In

order

to

ensure

long

DMAs

and

thus

validate

our

assumptions

on

effective

memory

bandwidth

we

adopted

an

approach

that

requires

two

full

element

transposes

First

N

N-point

FFTs

are

performed

for

the

rows

storing

the

data

back

to

DRAM

Second

the

data

stored

in

DRAM

is

transposed

-LRB-

columns

become

rows

-RRB-

and

stored

back

to

DRAM

Third

the

FFTs

are

performed

on

the

columns

whose

elements

are

now

sequential

-LRB-

because

of

the

transpose

-RRB-

Finally

a

second

transpose

is

applied

to

the

data

to

return

it

to

its

original

layout

Instead

of

performing

an

N

point

bit

reversal

for

every

FFT

entire

transformed

rows

-LRB-

not

the

elements

of

the

rows

-RRB-

are

stored

in

bit-reversed

order

-LRB-

in

effect

bit

reversing

the

elements

of

the

columns

-RRB-

After

the

first

transpose

a

decimation

in

frequency

FFT

is

applied

to

the

columns

The

columns

are

stored

back

in

bit-reversed

order

in

doing

so

the

row

elements

are

bit

reversed

With

a

final

transpose

the

data

is

stored

back

to

memory

in

natural

order

and

layout

in

less

time

Single

Precision

FFT

Performance

Table

presents

performance

results

for

the

Cell

and

FFT

For

the

case

more

than

half

of

the

total

time

is

spent

just

loading

and

storing

points

and

roots

of

unity

from

DRAM

If

completely

memory

bound

peak

performance

is

approximately

-LRB-

-RRB-

cycles

or

approximately

logN

Gflop/s

This

means

performance

is

limited

to

Gflop/s

for

a

point

SP

FFT

regardless

of

CPU

frequency

A

clear

area

for

future

exploration

is

hiding

computation

within

the

communication

and

the

minimiza-tion

of

the

overhead

involved

with

the

loading

of

the

roots

of

unity

Unfortunately

the

two

full

element

transposes

used

in

the

FFT

to

guarantee

long

sequential

accesses

consume

nearly

of

the

time

Thus

although

simultaneous

point

FFTs

achieve

Gflop/s

-LRB-

after

optimizing

away

the

loading

of

roots

of

unity

-RRB-

a

FFT

only

reaches

Gflop/s

an

impressive

figure

nonetheless

Without

the

bit

reversal

approach

the

performance

would

have

further

dropped

to

about

Gflop/s

The

smaller

FFT

's

shown

in

the

table

show

even

poorer

performance

Double

Precision

FFT

Performance

When

DP

is

employed

the

balance

between

memory

and

computation

is

changed

by

a

factor

of

This

pushes

a

Double

Precision

-LRB-

Gflop/s

-RRB-

N

Cell

pm

Cell

pm

Single

Precision

-LRB-

Gflop/s

-RRB-

N

Cell

pm

Cell

pm

Table

Performance

of

and

FFT

in

DP

-LRB-

top

-RRB-

and

SP

-LRB-

bottom

-RRB-

For

large

FFTs

Cell

is

more

than

times

faster

in

SP

than

either

the

Opteron

or

The

Gflop/s

number

is

calculated

based

on

a

naive

FFT

algorithm

For

FFTs

the

naive

algorithm

computes

N-point

FFTs

slightly

memory

bound

application

strongly

into

the

computationally

bound

domain

The

SP

simultaneous

FFT

is

times

faster

than

the

DP

version

On

the

upside

the

transposes

required

in

the

FFT

are

now

less

than

of

the

total

time

compared

with

for

the

SP

case

Cell

pm

finds

a

middle

ground

between

the

reduction

in

computational

throughput

and

the

increase

in

memory

traffic

increasing

performance

by

almost

x

compared

with

the

Cell

for

all

problem

sizes

Performance

Comparison

The

peak

Cell

FFT

performance

is

compared

to

a

number

of

other

processors

in

the

Table

These

results

are

conservative

given

the

naive

FFT

implementation

we

used

on

Cell

whereas

the

other

systems

in

the

comparison

used

highly

tuned

FFTW

-LSB-

-RSB-

or

vendor-tuned

FFT

implementations

-LSB-

-RSB-

Nonetheless

in

DP

Cell

pm

is

at

least

faster

than

the

for

a

FFT

and

Cell

pm

could

be

as

much

as

faster

for

a

large

FFT

Cell

more

than

doubles

the

DP

FFT

performance

of

Cell

for

all

problem

sizes

Cell

performance

is

nearly

at

parity

with

the

in

double

precision

however

we

believe

considerable

headroom

remains

for

more

sophisticated

Cell

FFT

implementations

In

single

precision

Cell

is

unparalleled

Note

that

FFT

performance

on

Cell

improves

as

the

number

of

points

increases

so

long

as

the

points

fit

within

the

local

store

In

comparison

the

performance

on

cache-based

machines

typically

reach

peak

at

a

problem

size

that

is

far

smaller

than

the

on-chip

cache-size

and

then

drops

precip-itously

once

the

associativity

of

the

cache

is

exhausted

and

cache

lines

start

getting

evicted

due

to

aliasing

Elimination

of

cache

evictions

requires

extensive

algorithmic

changes

for

the

power-of-two

problem

sizes

required

by

the

FFT

algorithm

but

such

evictions

will

not

occur

on

Cells

software-managed

local

store

Furthermore

we

believe

that

even

for

problems

that

are

larger

than

local

store

FFTs

will

con

FFT

numbers

provided

by

Cray

's

Bracy

Elton

and

Adrian

Tate

tinue

to

scale

much

better

on

Cell

than

typical

cache-based

superscalar

processors

with

set-associative

caches

since

local

store

provides

all

of

the

benefits

as

a

fully

associative

cache

The

FFT

performance

clearly

underscores

the

advantages

of

software-controlled

three-level

memory

architecture

over

conventional

cache-based

architectures

The

Cell

processor

offers

an

innovative

architectural

approach

that

will

be

produced

in

large

enough

volumes

to

be

cost-competitive

with

commodity

CPUs

This

work

presents

the

broadest

quantitative

study

Cell

's

performance

on

scientific

kernels

and

directly

compares

its

performance

to

tuned

kernels

running

on

leading

superscalar

-LRB-

Opteron

-RRB-

VLIW

-LRB-

-RRB-

and

vector

-LRB-

-RRB-

architectures

We

developed

an

analytic

framework

to

predict

Cell

performance

on

dense

and

sparse

matrix

operations

stencil

computations

and

and

FFTs

Using

this

approach

allowed

us

to

explore

numerous

algorithmic

approaches

without

the

effort

of

implementing

each

variation

We

believe

this

analytical

model

is

especially

important

given

the

relatively

immature

software

environment

makes

Cell

time-consuming

to

program

currently

the

model

proves

to

be

quite

accurate

because

the

programmer

has

explicit

control

over

parallelism

and

features

of

the

memory

system

Furthermore

we

propose

Cell

a

modest

architectural

variant

to

the

Cell

architecture

designed

to

improve

DP

behavior

Overall

results

demonstrate

the

tremendous

potential

of

the

Cell

architecture

for

scientific

computations

in

terms

of

both

raw

DP

and

SP

performance

and

power

efficiency

In

addition

we

show

that

Cell

significantly

out-performs

Cell

for

most

of

our

evaluated

DP

kernels

while

requiring

minimal

microarchitectural

modifications

to

the

existing

design

Analysis

shows

that

Cell

's

three

level

software-controlled

memory

architecture

which

completely

decouples

main

memory

load/store

from

computation

provides

several

advantages

over

mainstream

cache-based

architectures

First

kernel

performance

can

be

extremely

predictable

as

the

load

time

from

local

store

is

constant

Second

long

block

transfers

can

achieve

a

much

higher

percentage

of

memory

bandwidth

than

individual

loads

in

much

the

same

way

a

hardware

stream

prefetch

engine

once

engaged

can

fully

consume

memory

bandwidth

Finally

for

predictable

memory

access

patterns

communication

and

computation

can

be

overlapped

more

effectively

than

conventional

cache-based

approaches

Increasing

the

size

of

the

local

store

or

reducing

the

DMA

startup

overhead

on

future

Cell

implementations

may

further

enhance

the

scheduling

efficiency

by

enabling

more

effective

overlap

of

communication

and

computation

There

are

also

disadvantages

to

the

Cell

architecture

for

kernels

such

as

SpMV

With

its

lack

of

unaligned

load

support

Cell

must

issue

additional

instructions

simply

to

permute

data

yet

still

manages

to

outperform

conventional

scalar

processor

architectures

Even

memory

bandwidth

may

be

wasted

since

SpMV

is

constrained

to

use

tiling

to

remove

the

indirectly

indexed

accesses

to

the

source

vector

The

ability

however

to

perform

a

decoupled

gather

to

stream

nonzeros

and

Cell

's

low

functional

unit

latency

tends

to

hide

this

deficiency

Additionally

we

see

stencil

computations

as

an

example

of

an

algorithm

that

is

heavily

influenced

by

the

performance

of

the

permute

pipeline

Here

the

lack

of

support

for

an

unaligned

load

instruction

Speedup

vs.

Power

Efficiency

vs.

Cell

GEMM

x

x

x

x

SpMV

x

x

x

x

x

x

Stencil

x

x

x

x

x

x

FFT

x

x

x

x

x

x

FFT

x

x

x

x

x

x

Speedup

vs.

Power

Efficiency

vs.

Cell

GEMM

x

x

x

x

x

x

SpMV

x

x

x

x

x

x

Stencil

x

x

x

x

x

x

FFT

x

x

x

x

x

x

FFT

x

x

x

x

x

x

Table

Double

precision

speedup

and

increase

in

power

efficiency

of

-LRB-

Top

-RRB-

Cell

and

-LRB-

Bottom

-RRB-

Cell

relative

to

the

Opteron

and

for

our

evaluated

suite

of

scientific

kernels

Results

show

an

impressive

improvement

in

performance

and

power

efficiency

is

a

more

significant

performance

bottleneck

than

either

the

SP

execution

rate

or

the

memory

bandwidth

For

dense

matrix

operations

it

is

essential

to

maximize

computational

intensity

and

thereby

fully

utilize

the

local

store

However

if

not

done

properly

the

resulting

TLB

misses

adversely

affect

performance

For

example

in

the

GEMM

kernel

we

observe

that

the

BDL

data

storage

format

either

created

on

the

fly

or

before

hand

can

ensure

that

TLB

misses

remain

a

small

issue

even

as

on-chip

memories

increase

in

size

Table

compares

the

advantage

of

Cell

and

Cell

based

on

the

better

of

performance

model

or

actual

implementation

-LRB-

where

available

-RRB-

in

terms

of

DP

performance

and

power

efficiency

for

our

suite

of

evaluated

kernels

and

architectural

platforms

Observe

that

Cell

has

the

potential

to

greatly

increase

the

already

impressive

performance

characteristics

of

Cell

By

using

the

insight

gained

in

the

development

of

our

estimation

model

we

developed

an

optimized

SpMV

version

that

outperformed

our

initial

predictions

by

If

a

full

system

simulator

could

model

the

modest

improvements

of

our

Cell

variant

we

feel

confident

that

we

could

demonstrate

comparable

improvements

to

DP

performance

as

well

We

also

note

that

DP

stencil

performance

fell

short

of

our

model

by

due

to

previously

unknown

microarchitectural

limitations

However

time

skewing

showed

a

huge

benefit

in

SP

and

we

believe

a

similar

benefit

would

be

present

in

DP

on

Cell

variant

It

is

important

to

consider

these

performance

differences

in

the

context

of

increasingly

prevalent

multi-core

commodity

processors

The

first

generation

of

this

technology

will

instantiate

at

most

two

cores

per

chip

and

thus

will

deliver

less

than

twice

the

performance

of

today

's

existing

architectures

This

factor

of

is

trivial

compared

with

Cell

's

potential

of

improvement

While

peak

Cell

DP

performance

is

impressive

relative

to

its

commodity

peers

a

fully

utilizable

pipelined

DP

floating

point

unit

would

boost

Cell

-LRB-

i.e.

Cell

-RRB-

performance

and

efficiency

significantly

This

work

was

supported

by

the

Director

Office

of

Science

of

the

U.S.

Department

of

Energy

under

Contract

No

The

authors

gratefully

thank

Bracy

Elton

and

Adrian

Tate

for

their

assistance

in

obtaining

FFT

performance

data

and

Eduardo

D'Azevedo

for

providing

us

with

an

optimized

SpMV

implementation

-LSB-

-RSB-

G.

Blelloch

M.

Heroux

and

M.

Zagha

Segmented

operations

for

sparse

matrix

computation

on

vector

multiprocessors

Technical

Report

CMU

-LSB-

-RSB-

Cactus

homepage

-LSB-

-RSB-

L.

Cannon

A

Cellular

Computer

to

Implement

the

Kalman

Filter

Algorithm

PhD

thesis

Montana

State

University

-LSB-

-RSB-

Cell

broadband

engine

architecture

and

its

first

implementation

developerworks/power/library

pa-cellperf

-LSB-

-RSB-

Chombo

homepage

-LSB-

-RSB-

E.

D'Azevedo

M.

R.

Fahey

and

R.

T.

Mills

Vectorized

sparse

matrix

multiply

for

compressed

row

storage

format

In

International

Conference

on

Computational

Science

-LRB-

ICCS

-RRB-

pages

-LSB-

-RSB-

FFTW

speed

tests

-LSB-

-RSB-

B.

Flachs

S.

Asano

S.

Dhong

et

al.

A

streaming

processor

unit

for

a

cell

processor

ISSCC

Dig

Tech

Papers

pages

February

-LSB-

-RSB-

P.

Francesco

P.

Marchal

D.

Atienzaothers

et

al.

An

integrated

hardware/software

approach

for

run-time

scratchpad

management

In

Proceedings

of

the

Design

Automation

Conference

June

-LSB-

-RSB-

Ibm

cell

specifications

-LSB-

-RSB-

E.-J

Im

K.

Yelick

and

R.

Vuduc

Sparsity

Optimization

framework

for

sparse

matrix

kernels

International

Journal

of

High

Performance

Computing

Applications

-LSB-

-RSB-

The

Berkeley

Intelligent

RAM

-LRB-

IRAM

-RRB-

Project

-LSB-

-RSB-

G.

Jin

J.

Mellor-Crummey

and

R.

Fowlerothers

Increasing

temporal

locality

with

skewing

and

recursive

blocking

In

Proc

-LSB-

-RSB-

J.

Kahle

M.

Day

H.

Hofstee

et

al.

Introduction

to

the

cell

multiprocessor

IBM

Journal

of

R&D

-LRB-

-RRB-

-LSB-

-RSB-

S.

Kamil

P.

Husbands

L.

Oliker

et

al.

Impact

of

modern

memory

subsystems

on

cache

optimizations

for

stencil

computations

In

ACM

Workshop

on

Memory

System

Performance

June

-LSB-

-RSB-

M.

Kandemir

J.

Ramanujam

M.

Irwin

et

al.

Dynamic

management

of

scratch-pad

memory

space

In

Proceedings

of

the

Design

Automation

Conference

June

-LSB-

-RSB-

P.

Keltcher

S.

Richardson

S.

Siu

et

al.

An

equal

area

comparison

of

embedded

dram

and

sram

memory

architectures

for

a

chip

multiprocessor

Technical

report

HP

Laboratories

April

-LSB-

-RSB-

B.

Khailany

W.

Dally

S.

Rixner

et

al.

Imagine

Media

processing

with

streams

IEEE

Micro

-LRB-

-RRB-

March-April

-LSB-

-RSB-

M.

Kondo

H.

Okawara

H.

Nakamura

et

al.

Scima

A

novel

processor

architecture

for

high

performance

comp

uting

In

International

Conference

on

High

Performance

Computing

in

the

Asia

Pacific

Region

volume

May

-LSB-

-RSB-

A.

Kunimatsu

N.

Ide

T.

Sato

et

al.

Vector

unit

architecture

for

emotion

synthesis

IEEE

Micro

-LRB-

-RRB-

March

-LSB-

-RSB-

Z.

Li

and

Y.

Song

Automatic

tiling

of

iterative

stencil

loops

ACM

Transactions

on

Programming

Language

Systems

-LRB-

-RRB-

-LSB-

-RSB-

S.

Mueller

C.

Jacobi

C.

Hwa-Joon

et

al.

The

vector

floating-point

unit

in

a

synergistic

processor

element

of

a

cell

processor

In

IEEE

Annual

Symposium

on

Computer

Arithmetic

-LRB-

ISCA

-RRB-

June

-LSB-

-RSB-

M.

Oka

and

M.

Suzuoki

Designing

and

programming

the

emotion

engine

IEEE

Micro

-LRB-

-RRB-

November

-LSB-

-RSB-

L.

Oliker

R.

Biswas

J.

Borrill

et

al.

A

performance

evaluation

of

the

Cray

for

scientific

applications

In

Proc

International

Meeting

on

High

Performance

Computing

for

Computational

Science

-LSB-

-RSB-

Ornl

cray

evaluation

dunigan/cray

-LSB-

-RSB-

N.

Park

B.

Hong

and

V.

Prasanna

Analysis

of

memory

hierarchy

performance

of

block

data

layout

In

International

Conference

on

Parallel

Processing

-LRB-

ICPP

-RRB-

August

-LSB-

-RSB-

D.

Pham

S.

Asano

M.

Bollier

et

al.

The

design

and

implementation

of

a

first-generation

cell

processor

ISSCC

Dig

Tech

Papers

pages

February

-LSB-

-RSB-

Sony

press

release

-LSB-

-RSB-

M.

Suzuoki

et

al.

A

microprocessor

with

a

cpu

ten

floating

point

macs

four

floating-point

dividers

and

an

decoder

IEEE

Solid

State

Circuits

-LRB-

-RRB-

November

-LSB-

-RSB-

S.

Tomar

S.

Kim

N.

Vijaykrishnan

et

al.

Use

of

local

memory

for

efficient

java

execution

In

Proceedings

of

the

International

Conference

on

Computer

Design

September

-LSB-

-RSB-

R.

Vuduc

Automatic

Performance

Tuning

of

Sparse

Matrix

Kernels

PhD

thesis

University

of

California

at

Berkeley

-LSB-

-RSB-

D.

Wonnacott

Using

time

skewing

to

eliminate

idle

time

due

to

memory

bandwidth

and

network

limitations

In

International

Parallel

and

Distributed

Processing

Symposium

-LRB-

IPDPS

-RRB-

spmv
sparse matrix
stencil
gemm
cell processor
fft