/*******************************************************************************
* File Name: cyfitter.h
* 
* PSoC Creator  4.2
*
* Description:
* 
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice.h"
#include "cydevice_trm.h"

/* D1 */
#define D1__0__INTTYPE CYREG_PICU5_INTTYPE0
#define D1__0__MASK 0x01u
#define D1__0__PC CYREG_PRT5_PC0
#define D1__0__PORT 5u
#define D1__0__SHIFT 0u
#define D1__AG CYREG_PRT5_AG
#define D1__AMUX CYREG_PRT5_AMUX
#define D1__BIE CYREG_PRT5_BIE
#define D1__BIT_MASK CYREG_PRT5_BIT_MASK
#define D1__BYP CYREG_PRT5_BYP
#define D1__CTL CYREG_PRT5_CTL
#define D1__DM0 CYREG_PRT5_DM0
#define D1__DM1 CYREG_PRT5_DM1
#define D1__DM2 CYREG_PRT5_DM2
#define D1__DR CYREG_PRT5_DR
#define D1__INP_DIS CYREG_PRT5_INP_DIS
#define D1__INTSTAT CYREG_PICU5_INTSTAT
#define D1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU5_BASE
#define D1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define D1__LCD_EN CYREG_PRT5_LCD_EN
#define D1__MASK 0x01u
#define D1__PORT 5u
#define D1__PRT CYREG_PRT5_PRT
#define D1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define D1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define D1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define D1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define D1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define D1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define D1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define D1__PS CYREG_PRT5_PS
#define D1__SHIFT 0u
#define D1__SLW CYREG_PRT5_SLW
#define D1__SNAP CYREG_PICU5_SNAP

/* D2 */
#define D2__0__INTTYPE CYREG_PICU5_INTTYPE1
#define D2__0__MASK 0x02u
#define D2__0__PC CYREG_PRT5_PC1
#define D2__0__PORT 5u
#define D2__0__SHIFT 1u
#define D2__AG CYREG_PRT5_AG
#define D2__AMUX CYREG_PRT5_AMUX
#define D2__BIE CYREG_PRT5_BIE
#define D2__BIT_MASK CYREG_PRT5_BIT_MASK
#define D2__BYP CYREG_PRT5_BYP
#define D2__CTL CYREG_PRT5_CTL
#define D2__DM0 CYREG_PRT5_DM0
#define D2__DM1 CYREG_PRT5_DM1
#define D2__DM2 CYREG_PRT5_DM2
#define D2__DR CYREG_PRT5_DR
#define D2__INP_DIS CYREG_PRT5_INP_DIS
#define D2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU5_BASE
#define D2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define D2__LCD_EN CYREG_PRT5_LCD_EN
#define D2__MASK 0x02u
#define D2__PORT 5u
#define D2__PRT CYREG_PRT5_PRT
#define D2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define D2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define D2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define D2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define D2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define D2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define D2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define D2__PS CYREG_PRT5_PS
#define D2__SHIFT 1u
#define D2__SLW CYREG_PRT5_SLW

/* P2 */
#define P2__0__INTTYPE CYREG_PICU2_INTTYPE0
#define P2__0__MASK 0x01u
#define P2__0__PC CYREG_PRT2_PC0
#define P2__0__PORT 2u
#define P2__0__SHIFT 0u
#define P2__1__INTTYPE CYREG_PICU2_INTTYPE1
#define P2__1__MASK 0x02u
#define P2__1__PC CYREG_PRT2_PC1
#define P2__1__PORT 2u
#define P2__1__SHIFT 1u
#define P2__2__INTTYPE CYREG_PICU2_INTTYPE2
#define P2__2__MASK 0x04u
#define P2__2__PC CYREG_PRT2_PC2
#define P2__2__PORT 2u
#define P2__2__SHIFT 2u
#define P2__3__INTTYPE CYREG_PICU2_INTTYPE3
#define P2__3__MASK 0x08u
#define P2__3__PC CYREG_PRT2_PC3
#define P2__3__PORT 2u
#define P2__3__SHIFT 3u
#define P2__4__INTTYPE CYREG_PICU2_INTTYPE4
#define P2__4__MASK 0x10u
#define P2__4__PC CYREG_PRT2_PC4
#define P2__4__PORT 2u
#define P2__4__SHIFT 4u
#define P2__5__INTTYPE CYREG_PICU2_INTTYPE5
#define P2__5__MASK 0x20u
#define P2__5__PC CYREG_PRT2_PC5
#define P2__5__PORT 2u
#define P2__5__SHIFT 5u
#define P2__6__INTTYPE CYREG_PICU2_INTTYPE6
#define P2__6__MASK 0x40u
#define P2__6__PC CYREG_PRT2_PC6
#define P2__6__PORT 2u
#define P2__6__SHIFT 6u
#define P2__7__INTTYPE CYREG_PICU2_INTTYPE7
#define P2__7__MASK 0x80u
#define P2__7__PC CYREG_PRT2_PC7
#define P2__7__PORT 2u
#define P2__7__SHIFT 7u
#define P2__AG CYREG_PRT2_AG
#define P2__AMUX CYREG_PRT2_AMUX
#define P2__BIE CYREG_PRT2_BIE
#define P2__BIT_MASK CYREG_PRT2_BIT_MASK
#define P2__BYP CYREG_PRT2_BYP
#define P2__CTL CYREG_PRT2_CTL
#define P2__DM0 CYREG_PRT2_DM0
#define P2__DM1 CYREG_PRT2_DM1
#define P2__DM2 CYREG_PRT2_DM2
#define P2__DR CYREG_PRT2_DR
#define P2__INP_DIS CYREG_PRT2_INP_DIS
#define P2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE
#define P2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define P2__LCD_EN CYREG_PRT2_LCD_EN
#define P2__MASK 0xFFu
#define P2__PORT 2u
#define P2__PRT CYREG_PRT2_PRT
#define P2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define P2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define P2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define P2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define P2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define P2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define P2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define P2__PS CYREG_PRT2_PS
#define P2__SHIFT 0u
#define P2__SLW CYREG_PRT2_SLW

/* SW1 */
#define SW1__0__INTTYPE CYREG_PICU5_INTTYPE2
#define SW1__0__MASK 0x04u
#define SW1__0__PC CYREG_PRT5_PC2
#define SW1__0__PORT 5u
#define SW1__0__SHIFT 2u
#define SW1__AG CYREG_PRT5_AG
#define SW1__AMUX CYREG_PRT5_AMUX
#define SW1__BIE CYREG_PRT5_BIE
#define SW1__BIT_MASK CYREG_PRT5_BIT_MASK
#define SW1__BYP CYREG_PRT5_BYP
#define SW1__CTL CYREG_PRT5_CTL
#define SW1__DM0 CYREG_PRT5_DM0
#define SW1__DM1 CYREG_PRT5_DM1
#define SW1__DM2 CYREG_PRT5_DM2
#define SW1__DR CYREG_PRT5_DR
#define SW1__INP_DIS CYREG_PRT5_INP_DIS
#define SW1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU5_BASE
#define SW1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SW1__LCD_EN CYREG_PRT5_LCD_EN
#define SW1__MASK 0x04u
#define SW1__PORT 5u
#define SW1__PRT CYREG_PRT5_PRT
#define SW1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define SW1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define SW1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define SW1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define SW1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define SW1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SW1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SW1__PS CYREG_PRT5_PS
#define SW1__SHIFT 2u
#define SW1__SLW CYREG_PRT5_SLW

/* LED1 */
#define LED1__0__INTTYPE CYREG_PICU6_INTTYPE4
#define LED1__0__MASK 0x10u
#define LED1__0__PC CYREG_PRT6_PC4
#define LED1__0__PORT 6u
#define LED1__0__SHIFT 4u
#define LED1__AG CYREG_PRT6_AG
#define LED1__AMUX CYREG_PRT6_AMUX
#define LED1__BIE CYREG_PRT6_BIE
#define LED1__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED1__BYP CYREG_PRT6_BYP
#define LED1__CTL CYREG_PRT6_CTL
#define LED1__DM0 CYREG_PRT6_DM0
#define LED1__DM1 CYREG_PRT6_DM1
#define LED1__DM2 CYREG_PRT6_DM2
#define LED1__DR CYREG_PRT6_DR
#define LED1__INP_DIS CYREG_PRT6_INP_DIS
#define LED1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
#define LED1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED1__LCD_EN CYREG_PRT6_LCD_EN
#define LED1__MASK 0x10u
#define LED1__PORT 6u
#define LED1__PRT CYREG_PRT6_PRT
#define LED1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED1__PS CYREG_PRT6_PS
#define LED1__SHIFT 4u
#define LED1__SLW CYREG_PRT6_SLW

/* LED2 */
#define LED2__0__INTTYPE CYREG_PICU6_INTTYPE5
#define LED2__0__MASK 0x20u
#define LED2__0__PC CYREG_PRT6_PC5
#define LED2__0__PORT 6u
#define LED2__0__SHIFT 5u
#define LED2__AG CYREG_PRT6_AG
#define LED2__AMUX CYREG_PRT6_AMUX
#define LED2__BIE CYREG_PRT6_BIE
#define LED2__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED2__BYP CYREG_PRT6_BYP
#define LED2__CTL CYREG_PRT6_CTL
#define LED2__DM0 CYREG_PRT6_DM0
#define LED2__DM1 CYREG_PRT6_DM1
#define LED2__DM2 CYREG_PRT6_DM2
#define LED2__DR CYREG_PRT6_DR
#define LED2__INP_DIS CYREG_PRT6_INP_DIS
#define LED2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
#define LED2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED2__LCD_EN CYREG_PRT6_LCD_EN
#define LED2__MASK 0x20u
#define LED2__PORT 6u
#define LED2__PRT CYREG_PRT6_PRT
#define LED2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED2__PS CYREG_PRT6_PS
#define LED2__SHIFT 5u
#define LED2__SLW CYREG_PRT6_SLW

/* LED3 */
#define LED3__0__INTTYPE CYREG_PICU6_INTTYPE6
#define LED3__0__MASK 0x40u
#define LED3__0__PC CYREG_PRT6_PC6
#define LED3__0__PORT 6u
#define LED3__0__SHIFT 6u
#define LED3__AG CYREG_PRT6_AG
#define LED3__AMUX CYREG_PRT6_AMUX
#define LED3__BIE CYREG_PRT6_BIE
#define LED3__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED3__BYP CYREG_PRT6_BYP
#define LED3__CTL CYREG_PRT6_CTL
#define LED3__DM0 CYREG_PRT6_DM0
#define LED3__DM1 CYREG_PRT6_DM1
#define LED3__DM2 CYREG_PRT6_DM2
#define LED3__DR CYREG_PRT6_DR
#define LED3__INP_DIS CYREG_PRT6_INP_DIS
#define LED3__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
#define LED3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED3__LCD_EN CYREG_PRT6_LCD_EN
#define LED3__MASK 0x40u
#define LED3__PORT 6u
#define LED3__PRT CYREG_PRT6_PRT
#define LED3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED3__PS CYREG_PRT6_PS
#define LED3__SHIFT 6u
#define LED3__SLW CYREG_PRT6_SLW

/* LED4 */
#define LED4__0__INTTYPE CYREG_PICU6_INTTYPE7
#define LED4__0__MASK 0x80u
#define LED4__0__PC CYREG_PRT6_PC7
#define LED4__0__PORT 6u
#define LED4__0__SHIFT 7u
#define LED4__AG CYREG_PRT6_AG
#define LED4__AMUX CYREG_PRT6_AMUX
#define LED4__BIE CYREG_PRT6_BIE
#define LED4__BIT_MASK CYREG_PRT6_BIT_MASK
#define LED4__BYP CYREG_PRT6_BYP
#define LED4__CTL CYREG_PRT6_CTL
#define LED4__DM0 CYREG_PRT6_DM0
#define LED4__DM1 CYREG_PRT6_DM1
#define LED4__DM2 CYREG_PRT6_DM2
#define LED4__DR CYREG_PRT6_DR
#define LED4__INP_DIS CYREG_PRT6_INP_DIS
#define LED4__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE
#define LED4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define LED4__LCD_EN CYREG_PRT6_LCD_EN
#define LED4__MASK 0x80u
#define LED4__PORT 6u
#define LED4__PRT CYREG_PRT6_PRT
#define LED4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define LED4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define LED4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define LED4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define LED4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define LED4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define LED4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define LED4__PS CYREG_PRT6_PS
#define LED4__SHIFT 7u
#define LED4__SLW CYREG_PRT6_SLW

/* VDD1 */
#define VDD1__0__INTTYPE CYREG_PICU3_INTTYPE6
#define VDD1__0__MASK 0x40u
#define VDD1__0__PC CYREG_PRT3_PC6
#define VDD1__0__PORT 3u
#define VDD1__0__SHIFT 6u
#define VDD1__AG CYREG_PRT3_AG
#define VDD1__AMUX CYREG_PRT3_AMUX
#define VDD1__BIE CYREG_PRT3_BIE
#define VDD1__BIT_MASK CYREG_PRT3_BIT_MASK
#define VDD1__BYP CYREG_PRT3_BYP
#define VDD1__CTL CYREG_PRT3_CTL
#define VDD1__DM0 CYREG_PRT3_DM0
#define VDD1__DM1 CYREG_PRT3_DM1
#define VDD1__DM2 CYREG_PRT3_DM2
#define VDD1__DR CYREG_PRT3_DR
#define VDD1__INP_DIS CYREG_PRT3_INP_DIS
#define VDD1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define VDD1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define VDD1__LCD_EN CYREG_PRT3_LCD_EN
#define VDD1__MASK 0x40u
#define VDD1__PORT 3u
#define VDD1__PRT CYREG_PRT3_PRT
#define VDD1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define VDD1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define VDD1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define VDD1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define VDD1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define VDD1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define VDD1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define VDD1__PS CYREG_PRT3_PS
#define VDD1__SHIFT 6u
#define VDD1__SLW CYREG_PRT3_SLW

/* VDD2 */
#define VDD2__0__INTTYPE CYREG_PICU3_INTTYPE7
#define VDD2__0__MASK 0x80u
#define VDD2__0__PC CYREG_PRT3_PC7
#define VDD2__0__PORT 3u
#define VDD2__0__SHIFT 7u
#define VDD2__AG CYREG_PRT3_AG
#define VDD2__AMUX CYREG_PRT3_AMUX
#define VDD2__BIE CYREG_PRT3_BIE
#define VDD2__BIT_MASK CYREG_PRT3_BIT_MASK
#define VDD2__BYP CYREG_PRT3_BYP
#define VDD2__CTL CYREG_PRT3_CTL
#define VDD2__DM0 CYREG_PRT3_DM0
#define VDD2__DM1 CYREG_PRT3_DM1
#define VDD2__DM2 CYREG_PRT3_DM2
#define VDD2__DR CYREG_PRT3_DR
#define VDD2__INP_DIS CYREG_PRT3_INP_DIS
#define VDD2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define VDD2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define VDD2__LCD_EN CYREG_PRT3_LCD_EN
#define VDD2__MASK 0x80u
#define VDD2__PORT 3u
#define VDD2__PRT CYREG_PRT3_PRT
#define VDD2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define VDD2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define VDD2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define VDD2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define VDD2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define VDD2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define VDD2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define VDD2__PS CYREG_PRT3_PS
#define VDD2__SHIFT 7u
#define VDD2__SLW CYREG_PRT3_SLW

/* ADC_1 */
#define ADC_1_ADC_SAR__CLK CYREG_SAR0_CLK
#define ADC_1_ADC_SAR__CSR0 CYREG_SAR0_CSR0
#define ADC_1_ADC_SAR__CSR1 CYREG_SAR0_CSR1
#define ADC_1_ADC_SAR__CSR2 CYREG_SAR0_CSR2
#define ADC_1_ADC_SAR__CSR3 CYREG_SAR0_CSR3
#define ADC_1_ADC_SAR__CSR4 CYREG_SAR0_CSR4
#define ADC_1_ADC_SAR__CSR5 CYREG_SAR0_CSR5
#define ADC_1_ADC_SAR__CSR6 CYREG_SAR0_CSR6
#define ADC_1_ADC_SAR__PM_ACT_CFG CYREG_PM_ACT_CFG11
#define ADC_1_ADC_SAR__PM_ACT_MSK 0x01u
#define ADC_1_ADC_SAR__PM_STBY_CFG CYREG_PM_STBY_CFG11
#define ADC_1_ADC_SAR__PM_STBY_MSK 0x01u
#define ADC_1_ADC_SAR__SW0 CYREG_SAR0_SW0
#define ADC_1_ADC_SAR__SW2 CYREG_SAR0_SW2
#define ADC_1_ADC_SAR__SW3 CYREG_SAR0_SW3
#define ADC_1_ADC_SAR__SW4 CYREG_SAR0_SW4
#define ADC_1_ADC_SAR__SW6 CYREG_SAR0_SW6
#define ADC_1_ADC_SAR__TR0 CYREG_SAR0_TR0
#define ADC_1_ADC_SAR__WRK0 CYREG_SAR0_WRK0
#define ADC_1_ADC_SAR__WRK1 CYREG_SAR0_WRK1
#define ADC_1_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define ADC_1_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define ADC_1_IRQ__INTC_MASK 0x01u
#define ADC_1_IRQ__INTC_NUMBER 0u
#define ADC_1_IRQ__INTC_PRIOR_NUM 7u
#define ADC_1_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define ADC_1_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define ADC_1_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define ADC_1_theACLK__CFG0 CYREG_CLKDIST_ACFG1_CFG0
#define ADC_1_theACLK__CFG1 CYREG_CLKDIST_ACFG1_CFG1
#define ADC_1_theACLK__CFG2 CYREG_CLKDIST_ACFG1_CFG2
#define ADC_1_theACLK__CFG2_SRC_SEL_MASK 0x07u
#define ADC_1_theACLK__CFG3 CYREG_CLKDIST_ACFG1_CFG3
#define ADC_1_theACLK__CFG3_PHASE_DLY_MASK 0x0Fu
#define ADC_1_theACLK__INDEX 0x01u
#define ADC_1_theACLK__PM_ACT_CFG CYREG_PM_ACT_CFG1
#define ADC_1_theACLK__PM_ACT_MSK 0x02u
#define ADC_1_theACLK__PM_STBY_CFG CYREG_PM_STBY_CFG1
#define ADC_1_theACLK__PM_STBY_MSK 0x02u

/* ADC_2 */
#define ADC_2_ADC_SAR__CLK CYREG_SAR1_CLK
#define ADC_2_ADC_SAR__CSR0 CYREG_SAR1_CSR0
#define ADC_2_ADC_SAR__CSR1 CYREG_SAR1_CSR1
#define ADC_2_ADC_SAR__CSR2 CYREG_SAR1_CSR2
#define ADC_2_ADC_SAR__CSR3 CYREG_SAR1_CSR3
#define ADC_2_ADC_SAR__CSR4 CYREG_SAR1_CSR4
#define ADC_2_ADC_SAR__CSR5 CYREG_SAR1_CSR5
#define ADC_2_ADC_SAR__CSR6 CYREG_SAR1_CSR6
#define ADC_2_ADC_SAR__PM_ACT_CFG CYREG_PM_ACT_CFG11
#define ADC_2_ADC_SAR__PM_ACT_MSK 0x02u
#define ADC_2_ADC_SAR__PM_STBY_CFG CYREG_PM_STBY_CFG11
#define ADC_2_ADC_SAR__PM_STBY_MSK 0x02u
#define ADC_2_ADC_SAR__SW0 CYREG_SAR1_SW0
#define ADC_2_ADC_SAR__SW2 CYREG_SAR1_SW2
#define ADC_2_ADC_SAR__SW3 CYREG_SAR1_SW3
#define ADC_2_ADC_SAR__SW4 CYREG_SAR1_SW4
#define ADC_2_ADC_SAR__SW6 CYREG_SAR1_SW6
#define ADC_2_ADC_SAR__TR0 CYREG_SAR1_TR0
#define ADC_2_ADC_SAR__WRK0 CYREG_SAR1_WRK0
#define ADC_2_ADC_SAR__WRK1 CYREG_SAR1_WRK1
#define ADC_2_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define ADC_2_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define ADC_2_IRQ__INTC_MASK 0x02u
#define ADC_2_IRQ__INTC_NUMBER 1u
#define ADC_2_IRQ__INTC_PRIOR_NUM 7u
#define ADC_2_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define ADC_2_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define ADC_2_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define ADC_2_theACLK__CFG0 CYREG_CLKDIST_ACFG0_CFG0
#define ADC_2_theACLK__CFG1 CYREG_CLKDIST_ACFG0_CFG1
#define ADC_2_theACLK__CFG2 CYREG_CLKDIST_ACFG0_CFG2
#define ADC_2_theACLK__CFG2_SRC_SEL_MASK 0x07u
#define ADC_2_theACLK__CFG3 CYREG_CLKDIST_ACFG0_CFG3
#define ADC_2_theACLK__CFG3_PHASE_DLY_MASK 0x0Fu
#define ADC_2_theACLK__INDEX 0x00u
#define ADC_2_theACLK__PM_ACT_CFG CYREG_PM_ACT_CFG1
#define ADC_2_theACLK__PM_ACT_MSK 0x01u
#define ADC_2_theACLK__PM_STBY_CFG CYREG_PM_STBY_CFG1
#define ADC_2_theACLK__PM_STBY_MSK 0x01u

/* I2C_1 */
#define I2C_1_I2C_FF__ADR CYREG_I2C_ADR
#define I2C_1_I2C_FF__CFG CYREG_I2C_CFG
#define I2C_1_I2C_FF__CLK_DIV1 CYREG_I2C_CLK_DIV1
#define I2C_1_I2C_FF__CLK_DIV2 CYREG_I2C_CLK_DIV2
#define I2C_1_I2C_FF__CSR CYREG_I2C_CSR
#define I2C_1_I2C_FF__D CYREG_I2C_D
#define I2C_1_I2C_FF__MCSR CYREG_I2C_MCSR
#define I2C_1_I2C_FF__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define I2C_1_I2C_FF__PM_ACT_MSK 0x04u
#define I2C_1_I2C_FF__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define I2C_1_I2C_FF__PM_STBY_MSK 0x04u
#define I2C_1_I2C_FF__TMOUT_CFG0 CYREG_I2C_TMOUT_CFG0
#define I2C_1_I2C_FF__TMOUT_CFG1 CYREG_I2C_TMOUT_CFG1
#define I2C_1_I2C_FF__TMOUT_CSR CYREG_I2C_TMOUT_CSR
#define I2C_1_I2C_FF__TMOUT_SR CYREG_I2C_TMOUT_SR
#define I2C_1_I2C_FF__XCFG CYREG_I2C_XCFG
#define I2C_1_I2C_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define I2C_1_I2C_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define I2C_1_I2C_IRQ__INTC_MASK 0x8000u
#define I2C_1_I2C_IRQ__INTC_NUMBER 15u
#define I2C_1_I2C_IRQ__INTC_PRIOR_NUM 7u
#define I2C_1_I2C_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_15
#define I2C_1_I2C_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define I2C_1_I2C_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* SCL_1 */
#define SCL_1__0__INTTYPE CYREG_PICU12_INTTYPE4
#define SCL_1__0__MASK 0x10u
#define SCL_1__0__PC CYREG_PRT12_PC4
#define SCL_1__0__PORT 12u
#define SCL_1__0__SHIFT 4u
#define SCL_1__AG CYREG_PRT12_AG
#define SCL_1__BIE CYREG_PRT12_BIE
#define SCL_1__BIT_MASK CYREG_PRT12_BIT_MASK
#define SCL_1__BYP CYREG_PRT12_BYP
#define SCL_1__DM0 CYREG_PRT12_DM0
#define SCL_1__DM1 CYREG_PRT12_DM1
#define SCL_1__DM2 CYREG_PRT12_DM2
#define SCL_1__DR CYREG_PRT12_DR
#define SCL_1__INP_DIS CYREG_PRT12_INP_DIS
#define SCL_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define SCL_1__MASK 0x10u
#define SCL_1__PORT 12u
#define SCL_1__PRT CYREG_PRT12_PRT
#define SCL_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SCL_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SCL_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SCL_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SCL_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SCL_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SCL_1__PS CYREG_PRT12_PS
#define SCL_1__SHIFT 4u
#define SCL_1__SIO_CFG CYREG_PRT12_SIO_CFG
#define SCL_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SCL_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SCL_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SCL_1__SLW CYREG_PRT12_SLW

/* SDA_1 */
#define SDA_1__0__INTTYPE CYREG_PICU12_INTTYPE5
#define SDA_1__0__MASK 0x20u
#define SDA_1__0__PC CYREG_PRT12_PC5
#define SDA_1__0__PORT 12u
#define SDA_1__0__SHIFT 5u
#define SDA_1__AG CYREG_PRT12_AG
#define SDA_1__BIE CYREG_PRT12_BIE
#define SDA_1__BIT_MASK CYREG_PRT12_BIT_MASK
#define SDA_1__BYP CYREG_PRT12_BYP
#define SDA_1__DM0 CYREG_PRT12_DM0
#define SDA_1__DM1 CYREG_PRT12_DM1
#define SDA_1__DM2 CYREG_PRT12_DM2
#define SDA_1__DR CYREG_PRT12_DR
#define SDA_1__INP_DIS CYREG_PRT12_INP_DIS
#define SDA_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define SDA_1__MASK 0x20u
#define SDA_1__PORT 12u
#define SDA_1__PRT CYREG_PRT12_PRT
#define SDA_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SDA_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SDA_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SDA_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SDA_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SDA_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SDA_1__PS CYREG_PRT12_PS
#define SDA_1__SHIFT 5u
#define SDA_1__SIO_CFG CYREG_PRT12_SIO_CFG
#define SDA_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SDA_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SDA_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SDA_1__SLW CYREG_PRT12_SLW

/* isr_1 */
#define isr_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_1__INTC_MASK 0x200u
#define isr_1__INTC_NUMBER 9u
#define isr_1__INTC_PRIOR_NUM 7u
#define isr_1__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define isr_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* UART_1 */
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__5__MASK 0x20u
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__5__POS 5
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__6__MASK 0x40u
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__6__POS 6
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__7__MASK 0x80u
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__7__POS 7
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__CONTROL_REG CYREG_B0_UDB04_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__COUNT_REG CYREG_B0_UDB04_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__MASK 0xE0u
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sCR_SyncCtl_CtrlReg__PERIOD_REG CYREG_B0_UDB04_MSK
#define UART_1_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define UART_1_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define UART_1_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
#define UART_1_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define UART_1_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
#define UART_1_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
#define UART_1_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define UART_1_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
#define UART_1_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define UART_1_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define UART_1_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B0_UDB07_CTL
#define UART_1_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
#define UART_1_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B0_UDB07_CTL
#define UART_1_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
#define UART_1_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define UART_1_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define UART_1_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B0_UDB07_MSK
#define UART_1_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define UART_1_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define UART_1_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK
#define UART_1_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define UART_1_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define UART_1_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define UART_1_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
#define UART_1_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
#define UART_1_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
#define UART_1_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
#define UART_1_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
#define UART_1_BUART_sRX_RxShifter_u0__A0_REG CYREG_B1_UDB04_A0
#define UART_1_BUART_sRX_RxShifter_u0__A1_REG CYREG_B1_UDB04_A1
#define UART_1_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
#define UART_1_BUART_sRX_RxShifter_u0__D0_REG CYREG_B1_UDB04_D0
#define UART_1_BUART_sRX_RxShifter_u0__D1_REG CYREG_B1_UDB04_D1
#define UART_1_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define UART_1_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define UART_1_BUART_sRX_RxShifter_u0__F0_REG CYREG_B1_UDB04_F0
#define UART_1_BUART_sRX_RxShifter_u0__F1_REG CYREG_B1_UDB04_F1
#define UART_1_BUART_sRX_RxSts__0__MASK 0x01u
#define UART_1_BUART_sRX_RxSts__0__POS 0
#define UART_1_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define UART_1_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define UART_1_BUART_sRX_RxSts__3__MASK 0x08u
#define UART_1_BUART_sRX_RxSts__3__POS 3
#define UART_1_BUART_sRX_RxSts__4__MASK 0x10u
#define UART_1_BUART_sRX_RxSts__4__POS 4
#define UART_1_BUART_sRX_RxSts__5__MASK 0x20u
#define UART_1_BUART_sRX_RxSts__5__POS 5
#define UART_1_BUART_sRX_RxSts__6__MASK 0x40u
#define UART_1_BUART_sRX_RxSts__6__POS 6
#define UART_1_BUART_sRX_RxSts__MASK 0x79u
#define UART_1_BUART_sRX_RxSts__MASK_REG CYREG_B0_UDB04_MSK
#define UART_1_BUART_sRX_RxSts__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sRX_RxSts__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define UART_1_BUART_sRX_RxSts__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
#define UART_1_BUART_sRX_RxSts__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
#define UART_1_BUART_sRX_RxSts__STATUS_REG CYREG_B0_UDB04_ST
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB03_04_A0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB03_04_A1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB03_04_D0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB03_04_D1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB03_04_F0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB03_04_F1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB03_A0_A1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB03_A0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB03_A1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB03_D0_D1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB03_D0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB03_D1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB03_F0_F1
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB03_F0
#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB03_F1
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define UART_1_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB04_A0
#define UART_1_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB04_A1
#define UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define UART_1_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB04_D0
#define UART_1_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB04_D1
#define UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define UART_1_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB04_F0
#define UART_1_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB04_F1
#define UART_1_BUART_sTX_TxShifter_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sTX_TxShifter_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define UART_1_BUART_sTX_TxSts__0__MASK 0x01u
#define UART_1_BUART_sTX_TxSts__0__POS 0
#define UART_1_BUART_sTX_TxSts__1__MASK 0x02u
#define UART_1_BUART_sTX_TxSts__1__POS 1
#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
#define UART_1_BUART_sTX_TxSts__2__MASK 0x04u
#define UART_1_BUART_sTX_TxSts__2__POS 2
#define UART_1_BUART_sTX_TxSts__3__MASK 0x08u
#define UART_1_BUART_sTX_TxSts__3__POS 3
#define UART_1_BUART_sTX_TxSts__MASK 0x0Fu
#define UART_1_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB00_MSK
#define UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
#define UART_1_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB00_ST
#define UART_1_IntClock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define UART_1_IntClock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define UART_1_IntClock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define UART_1_IntClock__CFG2_SRC_SEL_MASK 0x07u
#define UART_1_IntClock__INDEX 0x02u
#define UART_1_IntClock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define UART_1_IntClock__PM_ACT_MSK 0x04u
#define UART_1_IntClock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define UART_1_IntClock__PM_STBY_MSK 0x04u
#define UART_1_Rx__0__INTTYPE CYREG_PICU12_INTTYPE0
#define UART_1_Rx__0__MASK 0x01u
#define UART_1_Rx__0__PC CYREG_PRT12_PC0
#define UART_1_Rx__0__PORT 12u
#define UART_1_Rx__0__SHIFT 0u
#define UART_1_Rx__AG CYREG_PRT12_AG
#define UART_1_Rx__BIE CYREG_PRT12_BIE
#define UART_1_Rx__BIT_MASK CYREG_PRT12_BIT_MASK
#define UART_1_Rx__BYP CYREG_PRT12_BYP
#define UART_1_Rx__DM0 CYREG_PRT12_DM0
#define UART_1_Rx__DM1 CYREG_PRT12_DM1
#define UART_1_Rx__DM2 CYREG_PRT12_DM2
#define UART_1_Rx__DR CYREG_PRT12_DR
#define UART_1_Rx__INP_DIS CYREG_PRT12_INP_DIS
#define UART_1_Rx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define UART_1_Rx__MASK 0x01u
#define UART_1_Rx__PORT 12u
#define UART_1_Rx__PRT CYREG_PRT12_PRT
#define UART_1_Rx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define UART_1_Rx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define UART_1_Rx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define UART_1_Rx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define UART_1_Rx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define UART_1_Rx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define UART_1_Rx__PS CYREG_PRT12_PS
#define UART_1_Rx__SHIFT 0u
#define UART_1_Rx__SIO_CFG CYREG_PRT12_SIO_CFG
#define UART_1_Rx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define UART_1_Rx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define UART_1_Rx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define UART_1_Rx__SLW CYREG_PRT12_SLW
#define UART_1_Tx__0__INTTYPE CYREG_PICU12_INTTYPE1
#define UART_1_Tx__0__MASK 0x02u
#define UART_1_Tx__0__PC CYREG_PRT12_PC1
#define UART_1_Tx__0__PORT 12u
#define UART_1_Tx__0__SHIFT 1u
#define UART_1_Tx__AG CYREG_PRT12_AG
#define UART_1_Tx__BIE CYREG_PRT12_BIE
#define UART_1_Tx__BIT_MASK CYREG_PRT12_BIT_MASK
#define UART_1_Tx__BYP CYREG_PRT12_BYP
#define UART_1_Tx__DM0 CYREG_PRT12_DM0
#define UART_1_Tx__DM1 CYREG_PRT12_DM1
#define UART_1_Tx__DM2 CYREG_PRT12_DM2
#define UART_1_Tx__DR CYREG_PRT12_DR
#define UART_1_Tx__INP_DIS CYREG_PRT12_INP_DIS
#define UART_1_Tx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define UART_1_Tx__MASK 0x02u
#define UART_1_Tx__PORT 12u
#define UART_1_Tx__PRT CYREG_PRT12_PRT
#define UART_1_Tx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define UART_1_Tx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define UART_1_Tx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define UART_1_Tx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define UART_1_Tx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define UART_1_Tx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define UART_1_Tx__PS CYREG_PRT12_PS
#define UART_1_Tx__SHIFT 1u
#define UART_1_Tx__SIO_CFG CYREG_PRT12_SIO_CFG
#define UART_1_Tx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define UART_1_Tx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define UART_1_Tx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define UART_1_Tx__SLW CYREG_PRT12_SLW

/* UART_2 */
#define UART_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define UART_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define UART_2_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
#define UART_2_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define UART_2_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
#define UART_2_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
#define UART_2_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define UART_2_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
#define UART_2_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define UART_2_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define UART_2_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B0_UDB02_CTL
#define UART_2_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
#define UART_2_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B0_UDB02_CTL
#define UART_2_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define UART_2_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define UART_2_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define UART_2_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B0_UDB02_MSK
#define UART_2_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define UART_2_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define UART_2_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B0_UDB02_MSK
#define UART_2_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define UART_2_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define UART_2_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define UART_2_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
#define UART_2_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
#define UART_2_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B0_UDB02_ST
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0
#define UART_2_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1
#define UART_2_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1
#define UART_2_BUART_sRX_RxShifter_u0__A0_REG CYREG_B1_UDB06_A0
#define UART_2_BUART_sRX_RxShifter_u0__A1_REG CYREG_B1_UDB06_A1
#define UART_2_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1
#define UART_2_BUART_sRX_RxShifter_u0__D0_REG CYREG_B1_UDB06_D0
#define UART_2_BUART_sRX_RxShifter_u0__D1_REG CYREG_B1_UDB06_D1
#define UART_2_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define UART_2_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1
#define UART_2_BUART_sRX_RxShifter_u0__F0_REG CYREG_B1_UDB06_F0
#define UART_2_BUART_sRX_RxShifter_u0__F1_REG CYREG_B1_UDB06_F1
#define UART_2_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define UART_2_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define UART_2_BUART_sRX_RxSts__3__MASK 0x08u
#define UART_2_BUART_sRX_RxSts__3__POS 3
#define UART_2_BUART_sRX_RxSts__4__MASK 0x10u
#define UART_2_BUART_sRX_RxSts__4__POS 4
#define UART_2_BUART_sRX_RxSts__5__MASK 0x20u
#define UART_2_BUART_sRX_RxSts__5__POS 5
#define UART_2_BUART_sRX_RxSts__MASK 0x38u
#define UART_2_BUART_sRX_RxSts__MASK_REG CYREG_B1_UDB06_MSK
#define UART_2_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define UART_2_BUART_sRX_RxSts__STATUS_REG CYREG_B1_UDB06_ST
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB01_02_A0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB01_02_A1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB01_02_D0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB01_02_D1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB01_02_F0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB01_02_F1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB01_A0_A1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB01_A0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB01_A1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB01_D0_D1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB01_D0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB01_D1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB01_F0_F1
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB01_F0
#define UART_2_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB01_F1
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB00_01_A0
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB00_01_A1
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB00_01_D0
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB00_01_D1
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB00_01_F0
#define UART_2_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB00_01_F1
#define UART_2_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB00_A0_A1
#define UART_2_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB00_A0
#define UART_2_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB00_A1
#define UART_2_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB00_D0_D1
#define UART_2_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB00_D0
#define UART_2_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB00_D1
#define UART_2_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL
#define UART_2_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB00_F0_F1
#define UART_2_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB00_F0
#define UART_2_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB00_F1
#define UART_2_BUART_sTX_TxSts__0__MASK 0x01u
#define UART_2_BUART_sTX_TxSts__0__POS 0
#define UART_2_BUART_sTX_TxSts__1__MASK 0x02u
#define UART_2_BUART_sTX_TxSts__1__POS 1
#define UART_2_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define UART_2_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
#define UART_2_BUART_sTX_TxSts__2__MASK 0x04u
#define UART_2_BUART_sTX_TxSts__2__POS 2
#define UART_2_BUART_sTX_TxSts__3__MASK 0x08u
#define UART_2_BUART_sTX_TxSts__3__POS 3
#define UART_2_BUART_sTX_TxSts__MASK 0x0Fu
#define UART_2_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB01_MSK
#define UART_2_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define UART_2_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB01_ST
#define UART_2_IntClock__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define UART_2_IntClock__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define UART_2_IntClock__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define UART_2_IntClock__CFG2_SRC_SEL_MASK 0x07u
#define UART_2_IntClock__INDEX 0x01u
#define UART_2_IntClock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define UART_2_IntClock__PM_ACT_MSK 0x02u
#define UART_2_IntClock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define UART_2_IntClock__PM_STBY_MSK 0x02u
#define UART_2_Rx__0__INTTYPE CYREG_PICU12_INTTYPE6
#define UART_2_Rx__0__MASK 0x40u
#define UART_2_Rx__0__PC CYREG_PRT12_PC6
#define UART_2_Rx__0__PORT 12u
#define UART_2_Rx__0__SHIFT 6u
#define UART_2_Rx__AG CYREG_PRT12_AG
#define UART_2_Rx__BIE CYREG_PRT12_BIE
#define UART_2_Rx__BIT_MASK CYREG_PRT12_BIT_MASK
#define UART_2_Rx__BYP CYREG_PRT12_BYP
#define UART_2_Rx__DM0 CYREG_PRT12_DM0
#define UART_2_Rx__DM1 CYREG_PRT12_DM1
#define UART_2_Rx__DM2 CYREG_PRT12_DM2
#define UART_2_Rx__DR CYREG_PRT12_DR
#define UART_2_Rx__INP_DIS CYREG_PRT12_INP_DIS
#define UART_2_Rx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define UART_2_Rx__MASK 0x40u
#define UART_2_Rx__PORT 12u
#define UART_2_Rx__PRT CYREG_PRT12_PRT
#define UART_2_Rx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define UART_2_Rx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define UART_2_Rx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define UART_2_Rx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define UART_2_Rx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define UART_2_Rx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define UART_2_Rx__PS CYREG_PRT12_PS
#define UART_2_Rx__SHIFT 6u
#define UART_2_Rx__SIO_CFG CYREG_PRT12_SIO_CFG
#define UART_2_Rx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define UART_2_Rx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define UART_2_Rx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define UART_2_Rx__SLW CYREG_PRT12_SLW
#define UART_2_Tx__0__INTTYPE CYREG_PICU12_INTTYPE7
#define UART_2_Tx__0__MASK 0x80u
#define UART_2_Tx__0__PC CYREG_PRT12_PC7
#define UART_2_Tx__0__PORT 12u
#define UART_2_Tx__0__SHIFT 7u
#define UART_2_Tx__AG CYREG_PRT12_AG
#define UART_2_Tx__BIE CYREG_PRT12_BIE
#define UART_2_Tx__BIT_MASK CYREG_PRT12_BIT_MASK
#define UART_2_Tx__BYP CYREG_PRT12_BYP
#define UART_2_Tx__DM0 CYREG_PRT12_DM0
#define UART_2_Tx__DM1 CYREG_PRT12_DM1
#define UART_2_Tx__DM2 CYREG_PRT12_DM2
#define UART_2_Tx__DR CYREG_PRT12_DR
#define UART_2_Tx__INP_DIS CYREG_PRT12_INP_DIS
#define UART_2_Tx__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define UART_2_Tx__MASK 0x80u
#define UART_2_Tx__PORT 12u
#define UART_2_Tx__PRT CYREG_PRT12_PRT
#define UART_2_Tx__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define UART_2_Tx__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define UART_2_Tx__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define UART_2_Tx__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define UART_2_Tx__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define UART_2_Tx__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define UART_2_Tx__PS CYREG_PRT12_PS
#define UART_2_Tx__SHIFT 7u
#define UART_2_Tx__SIO_CFG CYREG_PRT12_SIO_CFG
#define UART_2_Tx__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define UART_2_Tx__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define UART_2_Tx__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define UART_2_Tx__SLW CYREG_PRT12_SLW

/* Clock_1 */
#define Clock_1__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define Clock_1__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define Clock_1__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define Clock_1__CFG2_SRC_SEL_MASK 0x07u
#define Clock_1__INDEX 0x00u
#define Clock_1__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_1__PM_ACT_MSK 0x01u
#define Clock_1__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_1__PM_STBY_MSK 0x01u

/* USBUART */
#define USBUART_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_arb_int__INTC_MASK 0x400000u
#define USBUART_arb_int__INTC_NUMBER 22u
#define USBUART_arb_int__INTC_PRIOR_NUM 7u
#define USBUART_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
#define USBUART_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_bus_reset__INTC_MASK 0x800000u
#define USBUART_bus_reset__INTC_NUMBER 23u
#define USBUART_bus_reset__INTC_PRIOR_NUM 7u
#define USBUART_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
#define USBUART_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
#define USBUART_Dm__0__MASK 0x80u
#define USBUART_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBUART_Dm__0__PORT 15u
#define USBUART_Dm__0__SHIFT 7u
#define USBUART_Dm__AG CYREG_PRT15_AG
#define USBUART_Dm__AMUX CYREG_PRT15_AMUX
#define USBUART_Dm__BIE CYREG_PRT15_BIE
#define USBUART_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBUART_Dm__BYP CYREG_PRT15_BYP
#define USBUART_Dm__CTL CYREG_PRT15_CTL
#define USBUART_Dm__DM0 CYREG_PRT15_DM0
#define USBUART_Dm__DM1 CYREG_PRT15_DM1
#define USBUART_Dm__DM2 CYREG_PRT15_DM2
#define USBUART_Dm__DR CYREG_PRT15_DR
#define USBUART_Dm__INP_DIS CYREG_PRT15_INP_DIS
#define USBUART_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBUART_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBUART_Dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBUART_Dm__MASK 0x80u
#define USBUART_Dm__PORT 15u
#define USBUART_Dm__PRT CYREG_PRT15_PRT
#define USBUART_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBUART_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBUART_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBUART_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBUART_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBUART_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBUART_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBUART_Dm__PS CYREG_PRT15_PS
#define USBUART_Dm__SHIFT 7u
#define USBUART_Dm__SLW CYREG_PRT15_SLW
#define USBUART_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
#define USBUART_Dp__0__MASK 0x40u
#define USBUART_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBUART_Dp__0__PORT 15u
#define USBUART_Dp__0__SHIFT 6u
#define USBUART_Dp__AG CYREG_PRT15_AG
#define USBUART_Dp__AMUX CYREG_PRT15_AMUX
#define USBUART_Dp__BIE CYREG_PRT15_BIE
#define USBUART_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBUART_Dp__BYP CYREG_PRT15_BYP
#define USBUART_Dp__CTL CYREG_PRT15_CTL
#define USBUART_Dp__DM0 CYREG_PRT15_DM0
#define USBUART_Dp__DM1 CYREG_PRT15_DM1
#define USBUART_Dp__DM2 CYREG_PRT15_DM2
#define USBUART_Dp__DR CYREG_PRT15_DR
#define USBUART_Dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBUART_Dp__INTSTAT CYREG_PICU15_INTSTAT
#define USBUART_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBUART_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBUART_Dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBUART_Dp__MASK 0x40u
#define USBUART_Dp__PORT 15u
#define USBUART_Dp__PRT CYREG_PRT15_PRT
#define USBUART_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBUART_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBUART_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBUART_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBUART_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBUART_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBUART_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBUART_Dp__PS CYREG_PRT15_PS
#define USBUART_Dp__SHIFT 6u
#define USBUART_Dp__SLW CYREG_PRT15_SLW
#define USBUART_Dp__SNAP CYREG_PICU_15_SNAP_15
#define USBUART_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_dp_int__INTC_MASK 0x1000u
#define USBUART_dp_int__INTC_NUMBER 12u
#define USBUART_dp_int__INTC_PRIOR_NUM 7u
#define USBUART_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
#define USBUART_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_ep_0__INTC_MASK 0x1000000u
#define USBUART_ep_0__INTC_NUMBER 24u
#define USBUART_ep_0__INTC_PRIOR_NUM 7u
#define USBUART_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
#define USBUART_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_ep_1__INTC_MASK 0x04u
#define USBUART_ep_1__INTC_NUMBER 2u
#define USBUART_ep_1__INTC_PRIOR_NUM 7u
#define USBUART_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_2
#define USBUART_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_ep_2__INTC_MASK 0x08u
#define USBUART_ep_2__INTC_NUMBER 3u
#define USBUART_ep_2__INTC_PRIOR_NUM 7u
#define USBUART_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define USBUART_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_ep_3__INTC_MASK 0x10u
#define USBUART_ep_3__INTC_NUMBER 4u
#define USBUART_ep_3__INTC_PRIOR_NUM 7u
#define USBUART_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define USBUART_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBUART_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBUART_sof_int__INTC_MASK 0x200000u
#define USBUART_sof_int__INTC_NUMBER 21u
#define USBUART_sof_int__INTC_PRIOR_NUM 7u
#define USBUART_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
#define USBUART_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBUART_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBUART_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBUART_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
#define USBUART_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
#define USBUART_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
#define USBUART_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
#define USBUART_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
#define USBUART_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
#define USBUART_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
#define USBUART_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
#define USBUART_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
#define USBUART_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
#define USBUART_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
#define USBUART_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
#define USBUART_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
#define USBUART_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
#define USBUART_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
#define USBUART_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
#define USBUART_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
#define USBUART_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
#define USBUART_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
#define USBUART_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
#define USBUART_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
#define USBUART_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
#define USBUART_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
#define USBUART_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
#define USBUART_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
#define USBUART_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
#define USBUART_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
#define USBUART_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
#define USBUART_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
#define USBUART_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
#define USBUART_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
#define USBUART_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
#define USBUART_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
#define USBUART_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
#define USBUART_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
#define USBUART_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
#define USBUART_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
#define USBUART_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
#define USBUART_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
#define USBUART_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
#define USBUART_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
#define USBUART_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
#define USBUART_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
#define USBUART_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
#define USBUART_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
#define USBUART_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
#define USBUART_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
#define USBUART_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
#define USBUART_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
#define USBUART_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
#define USBUART_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
#define USBUART_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
#define USBUART_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
#define USBUART_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
#define USBUART_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
#define USBUART_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
#define USBUART_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
#define USBUART_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
#define USBUART_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
#define USBUART_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
#define USBUART_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
#define USBUART_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
#define USBUART_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
#define USBUART_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
#define USBUART_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
#define USBUART_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
#define USBUART_USB__BUF_SIZE CYREG_USB_BUF_SIZE
#define USBUART_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
#define USBUART_USB__CR0 CYREG_USB_CR0
#define USBUART_USB__CR1 CYREG_USB_CR1
#define USBUART_USB__CWA CYREG_USB_CWA
#define USBUART_USB__CWA_MSB CYREG_USB_CWA_MSB
#define USBUART_USB__DMA_THRES CYREG_USB_DMA_THRES
#define USBUART_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
#define USBUART_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
#define USBUART_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
#define USBUART_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBUART_USB__EP0_CNT CYREG_USB_EP0_CNT
#define USBUART_USB__EP0_CR CYREG_USB_EP0_CR
#define USBUART_USB__EP0_DR0 CYREG_USB_EP0_DR0
#define USBUART_USB__EP0_DR1 CYREG_USB_EP0_DR1
#define USBUART_USB__EP0_DR2 CYREG_USB_EP0_DR2
#define USBUART_USB__EP0_DR3 CYREG_USB_EP0_DR3
#define USBUART_USB__EP0_DR4 CYREG_USB_EP0_DR4
#define USBUART_USB__EP0_DR5 CYREG_USB_EP0_DR5
#define USBUART_USB__EP0_DR6 CYREG_USB_EP0_DR6
#define USBUART_USB__EP0_DR7 CYREG_USB_EP0_DR7
#define USBUART_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
#define USBUART_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define USBUART_USB__PM_ACT_MSK 0x01u
#define USBUART_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define USBUART_USB__PM_STBY_MSK 0x01u
#define USBUART_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
#define USBUART_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBUART_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
#define USBUART_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
#define USBUART_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
#define USBUART_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
#define USBUART_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
#define USBUART_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
#define USBUART_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
#define USBUART_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
#define USBUART_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
#define USBUART_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
#define USBUART_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
#define USBUART_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
#define USBUART_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
#define USBUART_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
#define USBUART_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
#define USBUART_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
#define USBUART_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
#define USBUART_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
#define USBUART_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
#define USBUART_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
#define USBUART_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
#define USBUART_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
#define USBUART_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
#define USBUART_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
#define USBUART_USB__SOF0 CYREG_USB_SOF0
#define USBUART_USB__SOF1 CYREG_USB_SOF1
#define USBUART_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
#define USBUART_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBUART_USB__USBIO_CR1 CYREG_USB_USBIO_CR1

/* isr_Tick */
#define isr_Tick__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_Tick__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_Tick__INTC_MASK 0x40u
#define isr_Tick__INTC_NUMBER 6u
#define isr_Tick__INTC_PRIOR_NUM 7u
#define isr_Tick__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define isr_Tick__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_Tick__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* Clock_Tick */
#define Clock_Tick__CFG0 CYREG_CLKDIST_DCFG3_CFG0
#define Clock_Tick__CFG1 CYREG_CLKDIST_DCFG3_CFG1
#define Clock_Tick__CFG2 CYREG_CLKDIST_DCFG3_CFG2
#define Clock_Tick__CFG2_SRC_SEL_MASK 0x07u
#define Clock_Tick__INDEX 0x03u
#define Clock_Tick__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_Tick__PM_ACT_MSK 0x08u
#define Clock_Tick__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_Tick__PM_STBY_MSK 0x08u

/* isr_UART_1_Rx */
#define isr_UART_1_Rx__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_UART_1_Rx__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_UART_1_Rx__INTC_MASK 0x80u
#define isr_UART_1_Rx__INTC_NUMBER 7u
#define isr_UART_1_Rx__INTC_PRIOR_NUM 7u
#define isr_UART_1_Rx__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define isr_UART_1_Rx__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_UART_1_Rx__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_UART_1_Tx */
#define isr_UART_1_Tx__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_UART_1_Tx__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_UART_1_Tx__INTC_MASK 0x100u
#define isr_UART_1_Tx__INTC_NUMBER 8u
#define isr_UART_1_Tx__INTC_PRIOR_NUM 7u
#define isr_UART_1_Tx__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define isr_UART_1_Tx__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_UART_1_Tx__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_UART_2_Rx */
#define isr_UART_2_Rx__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_UART_2_Rx__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_UART_2_Rx__INTC_MASK 0x400u
#define isr_UART_2_Rx__INTC_NUMBER 10u
#define isr_UART_2_Rx__INTC_PRIOR_NUM 7u
#define isr_UART_2_Rx__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define isr_UART_2_Rx__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_UART_2_Rx__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_UART_2_Tx */
#define isr_UART_2_Tx__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_UART_2_Tx__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_UART_2_Tx__INTC_MASK 0x800u
#define isr_UART_2_Tx__INTC_NUMBER 11u
#define isr_UART_2_Tx__INTC_PRIOR_NUM 7u
#define isr_UART_2_Tx__INTC_PRIOR_REG CYREG_NVIC_PRI_11
#define isr_UART_2_Tx__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_UART_2_Tx__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* isr_SleepTimer */
#define isr_SleepTimer__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define isr_SleepTimer__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define isr_SleepTimer__INTC_MASK 0x20u
#define isr_SleepTimer__INTC_NUMBER 5u
#define isr_SleepTimer__INTC_PRIOR_NUM 7u
#define isr_SleepTimer__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define isr_SleepTimer__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define isr_SleepTimer__INTC_SET_PD_REG CYREG_NVIC_SETPEND0

/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 24000000U
#define BCLK__BUS_CLK__KHZ 24000U
#define BCLK__BUS_CLK__MHZ 24U
#define CY_PROJECT_NAME "Design01"
#define CY_VERSION "PSoC Creator  4.2"
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 18u
#define CYDEV_CHIP_DIE_PSOC5LP 2u
#define CYDEV_CHIP_DIE_PSOC5TM 3u
#define CYDEV_CHIP_DIE_TMA4 4u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 5u
#define CYDEV_CHIP_FAMILY_FM3 6u
#define CYDEV_CHIP_FAMILY_FM4 7u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_PSOC6 4u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E160069u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 18u
#define CYDEV_CHIP_MEMBER_4D 13u
#define CYDEV_CHIP_MEMBER_4E 6u
#define CYDEV_CHIP_MEMBER_4F 19u
#define CYDEV_CHIP_MEMBER_4G 4u
#define CYDEV_CHIP_MEMBER_4H 17u
#define CYDEV_CHIP_MEMBER_4I 23u
#define CYDEV_CHIP_MEMBER_4J 14u
#define CYDEV_CHIP_MEMBER_4K 15u
#define CYDEV_CHIP_MEMBER_4L 22u
#define CYDEV_CHIP_MEMBER_4M 21u
#define CYDEV_CHIP_MEMBER_4N 10u
#define CYDEV_CHIP_MEMBER_4O 7u
#define CYDEV_CHIP_MEMBER_4P 20u
#define CYDEV_CHIP_MEMBER_4Q 12u
#define CYDEV_CHIP_MEMBER_4R 8u
#define CYDEV_CHIP_MEMBER_4S 11u
#define CYDEV_CHIP_MEMBER_4T 9u
#define CYDEV_CHIP_MEMBER_4U 5u
#define CYDEV_CHIP_MEMBER_4V 16u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 2u
#define CYDEV_CHIP_MEMBER_6A 24u
#define CYDEV_CHIP_MEMBER_FM3 28u
#define CYDEV_CHIP_MEMBER_FM4 29u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_6A_ES 17u
#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u
#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x400
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00008DC3u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5
#define CYDEV_VIO3_MV 5000
#define CYIPBLOCK_ARM_CM3_VERSION 0
#define CYIPBLOCK_P3_ANAIF_VERSION 0
#define CYIPBLOCK_P3_CAN_VERSION 0
#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
#define CYIPBLOCK_P3_COMP_VERSION 0
#define CYIPBLOCK_P3_DECIMATOR_VERSION 0
#define CYIPBLOCK_P3_DFB_VERSION 0
#define CYIPBLOCK_P3_DMA_VERSION 0
#define CYIPBLOCK_P3_DRQ_VERSION 0
#define CYIPBLOCK_P3_DSM_VERSION 0
#define CYIPBLOCK_P3_EMIF_VERSION 0
#define CYIPBLOCK_P3_I2C_VERSION 0
#define CYIPBLOCK_P3_LCD_VERSION 0
#define CYIPBLOCK_P3_LPF_VERSION 0
#define CYIPBLOCK_P3_OPAMP_VERSION 0
#define CYIPBLOCK_P3_PM_VERSION 0
#define CYIPBLOCK_P3_SCCT_VERSION 0
#define CYIPBLOCK_P3_TIMER_VERSION 0
#define CYIPBLOCK_P3_USB_VERSION 0
#define CYIPBLOCK_P3_VIDAC_VERSION 0
#define CYIPBLOCK_P3_VREF_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 0
#define CYIPBLOCK_S8_IRQ_VERSION 0
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
