/*******************************************************************************
 *
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * Use of the Software is limited solely to applications:
 * (a) running on a Xilinx device, or
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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*******************************************************************************/
/******************************************************************************/
/**
 *
 * @file xvphy_hdmi.h
 *
 * The Xilinx Video PHY (VPHY) driver. This driver supports the Xilinx Video PHY
 * IP core.
 *
 * @note	None.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.0   vkd  10/19/15 Initial release.
 * </pre>
 *
 * @addtogroup xvphy
 * @{
*******************************************************************************/

#ifndef XVPHY_DP_H_
/* Prevent circular inclusions by using protection macros. */
#define XVPHY_DP_H_

/************************** Constant Definitions ******************************/

/* GTXE2. */
#define XVPHY_GTXE2_DIFF_SWING_DP_L0		0x03
#define XVPHY_GTXE2_DIFF_SWING_DP_L1		0x06
#define XVPHY_GTXE2_DIFF_SWING_DP_L2		0x09
#define XVPHY_GTXE2_DIFF_SWING_DP_L3		0x0F

#define XVPHY_GTXE2_PREEMP_DP_L0		0x00
#define XVPHY_GTXE2_PREEMP_DP_L1		0x0E
#define XVPHY_GTXE2_PREEMP_DP_L2		0x14
#define XVPHY_GTXE2_PREEMP_DP_L3		0x14

/* GTHE3. */
#define XVPHY_GTHE3_DIFF_SWING_DP_L0		0x03
#define XVPHY_GTHE3_DIFF_SWING_DP_L1		0x06
#define XVPHY_GTHE3_DIFF_SWING_DP_L2		0x09
#define XVPHY_GTHE3_DIFF_SWING_DP_L3		0x0F

#define XVPHY_GTHE3_PREEMP_DP_L0		0x00
#define XVPHY_GTHE3_PREEMP_DP_L1		0x0E
#define XVPHY_GTHE3_PREEMP_DP_L2		0x14
#define XVPHY_GTHE3_PREEMP_DP_L3		0x14

/* DP line rate coding. */
#define XVPHY_DP_LINK_BW_SET_162GBPS		0x06
#define XVPHY_DP_LINK_BW_SET_270GBPS		0x0A
#define XVPHY_DP_LINK_BW_SET_540GBPS		0x14

#define XVPHY_DP_LINK_RATE_HZ_162GBPS	1620000000LL
#define XVPHY_DP_LINK_RATE_HZ_270GBPS	2700000000LL
#define XVPHY_DP_LINK_RATE_HZ_540GBPS	5400000000LL

#define XVPHY_DP_REF_CLK_FREQ_HZ_162	 162000000LL
#define XVPHY_DP_REF_CLK_FREQ_HZ_135	 135000000LL
#define XVPHY_DP_REF_CLK_FREQ_HZ_81	  81000000LL
#define XVPHY_DP_REF_CLK_FREQ_HZ_270	 270000000LL

#endif /* XVPHY_HDMI_H_ */
/** @} */