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* Copyright (C) 2010-2019 Xilinx, Inc. All rights reserved.
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*of this software and associated documentation files (the "Software"), to deal
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*furnished to do so, subject to the following conditions:
*
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*all copies or substantial portions of the Software.
*
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#include "xparameters.h"
#include "xzdma.h"

/*
* The configuration table for devices
*/

XZDma_Config XZDma_ConfigTable[] =
{
	{
		XPAR_PSU_ADMA_CH0_DEVICE_ID,
		XPAR_PSU_ADMA_CH0_BASEADDR,
		XPAR_PSU_ADMA_CH0_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH1_DEVICE_ID,
		XPAR_PSU_ADMA_CH1_BASEADDR,
		XPAR_PSU_ADMA_CH1_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH2_DEVICE_ID,
		XPAR_PSU_ADMA_CH2_BASEADDR,
		XPAR_PSU_ADMA_CH2_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH3_DEVICE_ID,
		XPAR_PSU_ADMA_CH3_BASEADDR,
		XPAR_PSU_ADMA_CH3_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH4_DEVICE_ID,
		XPAR_PSU_ADMA_CH4_BASEADDR,
		XPAR_PSU_ADMA_CH4_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH5_DEVICE_ID,
		XPAR_PSU_ADMA_CH5_BASEADDR,
		XPAR_PSU_ADMA_CH5_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH6_DEVICE_ID,
		XPAR_PSU_ADMA_CH6_BASEADDR,
		XPAR_PSU_ADMA_CH6_DMA_MODE
	},
	{
		XPAR_PSU_ADMA_CH7_DEVICE_ID,
		XPAR_PSU_ADMA_CH7_BASEADDR,
		XPAR_PSU_ADMA_CH7_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH0_DEVICE_ID,
		XPAR_PSU_GDMA_CH0_BASEADDR,
		XPAR_PSU_GDMA_CH0_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH1_DEVICE_ID,
		XPAR_PSU_GDMA_CH1_BASEADDR,
		XPAR_PSU_GDMA_CH1_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH2_DEVICE_ID,
		XPAR_PSU_GDMA_CH2_BASEADDR,
		XPAR_PSU_GDMA_CH2_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH3_DEVICE_ID,
		XPAR_PSU_GDMA_CH3_BASEADDR,
		XPAR_PSU_GDMA_CH3_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH4_DEVICE_ID,
		XPAR_PSU_GDMA_CH4_BASEADDR,
		XPAR_PSU_GDMA_CH4_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH5_DEVICE_ID,
		XPAR_PSU_GDMA_CH5_BASEADDR,
		XPAR_PSU_GDMA_CH5_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH6_DEVICE_ID,
		XPAR_PSU_GDMA_CH6_BASEADDR,
		XPAR_PSU_GDMA_CH6_DMA_MODE
	},
	{
		XPAR_PSU_GDMA_CH7_DEVICE_ID,
		XPAR_PSU_GDMA_CH7_BASEADDR,
		XPAR_PSU_GDMA_CH7_DMA_MODE
	}
};
