/********************************************************************
*
* R5FSS1_CORE1 INTERRUPT MAP. header file
*
* Copyright (C) 2015-2019 Texas Instruments Incorporated.
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef CSLR_R5FSS1_CORE1_INTERRUPT_MAP_H_
#define CSLR_R5FSS1_CORE1_INTERRUPT_MAP_H_

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>
#ifdef __cplusplus
extern "C"
{
#endif

/*
* List of intr sources for receiver: R5FSS1_CORE1
*/

#define CSLR_R5FSS1_CORE1_INTR_CTRL_MMR0_IPC_SET18_IPC_SET_IPCFG_0                                 (0U)
#define CSLR_R5FSS1_CORE1_INTR_CTRL_MMR0_IPC_SET19_IPC_SET_IPCFG_0                                 (1U)
#define CSLR_R5FSS1_CORE1_INTR_RTI30_INTR_WWD_0                                                    (2U)
#define CSLR_R5FSS1_CORE1_INTR_RTI31_INTR_WWD_0                                                    (3U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_COMMRX_LEVEL_1_0                                             (4U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_COMMTX_LEVEL_1_0                                             (5U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE1_VALFIQ_0                                               (6U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE1_VALIRQ_0                                               (7U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE0_CTI_0                                                  (8U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE1_CTI_0                                                  (9U)
#define CSLR_R5FSS1_CORE1_INTR_ESM0_ESM_INT_LOW_LVL_0                                              (10U)
#define CSLR_R5FSS1_CORE1_INTR_ESM0_ESM_INT_HI_LVL_0                                               (11U)
#define CSLR_R5FSS1_CORE1_INTR_ESM0_ESM_INT_CFG_LVL_0                                              (12U)
#define CSLR_R5FSS1_CORE1_INTR_GLUELOGIC_EXT_INTN_GLUE_EXT_INT_LVL_0                               (13U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE0_EXP_INTR_0                                             (16U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_CORE1_EXP_INTR_0                                             (17U)
#define CSLR_R5FSS1_CORE1_INTR_DMPAC0_INTD_0_SYSTEM_INTR_LEVEL_0                                   (32U)
#define CSLR_R5FSS1_CORE1_INTR_DMPAC0_INTD_0_SYSTEM_INTR_LEVEL_1                                   (33U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_0                                    (34U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_1                                    (35U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_2                                    (36U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_3                                    (37U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_4                                    (38U)
#define CSLR_R5FSS1_CORE1_INTR_VPAC0_INTD_0_SYSTEM_INTR_LEVEL_5                                    (39U)
#define CSLR_R5FSS1_CORE1_INTR_GPU0_MISC_0_IRQ_0                                                   (40U)
#define CSLR_R5FSS1_CORE1_INTR_GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_REQINT_LVL_0                (48U)
#define CSLR_R5FSS1_CORE1_INTR_GLUELOGIC_GPU_GPIO_REQACK_GLUE_GPU_GPIO_ACKINT_LVL_0                (49U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_FUNC_IRQ_PROC0_0                               (52U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_FUNC_IRQ_PROC1_0                               (53U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_SAFETY_ERROR_IRQ_PROC0_0                       (54U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_SAFETY_ERROR_IRQ_PROC1_0                       (55U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_SECURE_IRQ_PROC0_0                             (56U)
#define CSLR_R5FSS1_CORE1_INTR_DSS0_DSS_INST0_DISPC_SECURE_IRQ_PROC1_0                             (57U)
#define CSLR_R5FSS1_CORE1_INTR_DSS_EDP0_INTR_0                                                     (64U)
#define CSLR_R5FSS1_CORE1_INTR_DSS_EDP0_INTR_1                                                     (65U)
#define CSLR_R5FSS1_CORE1_INTR_DSS_EDP0_INTR_2                                                     (66U)
#define CSLR_R5FSS1_CORE1_INTR_DSS_EDP0_INTR_3                                                     (67U)
#define CSLR_R5FSS1_CORE1_INTR_DSS_DSI0_DSI_0_FUNC_INTR_0                                          (76U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF0_CSI_ERR_IRQ_0                                            (78U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF0_CSI_IRQ_0                                                (79U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF0_CSI_LEVEL_0                                              (80U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF1_CSI_ERR_IRQ_0                                            (81U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF1_CSI_IRQ_0                                                (82U)
#define CSLR_R5FSS1_CORE1_INTR_CSI_RX_IF1_CSI_LEVEL_0                                              (83U)
#define CSLR_R5FSS1_CORE1_INTR_DECODER0_IRQ_0                                                      (87U)
#define CSLR_R5FSS1_CORE1_INTR_ENCODER0_IRQ_0                                                      (88U)
#define CSLR_R5FSS1_CORE1_INTR_CPSW0_STAT_PEND_0                                                   (96U)
#define CSLR_R5FSS1_CORE1_INTR_CPSW0_MDIO_PEND_0                                                   (97U)
#define CSLR_R5FSS1_CORE1_INTR_CPSW0_EVNT_PEND_0                                                   (98U)
#define CSLR_R5FSS1_CORE1_INTR_MMCSD0_EMMCSS_INTR_0                                                (99U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM0_EPWM_ETINT_0                                                (104U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM1_EPWM_ETINT_0                                                (105U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM2_EPWM_ETINT_0                                                (106U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM3_EPWM_ETINT_0                                                (107U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM4_EPWM_ETINT_0                                                (108U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM5_EPWM_ETINT_0                                                (109U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM0_EPWM_TRIPZINT_0                                             (110U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM1_EPWM_TRIPZINT_0                                             (111U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM2_EPWM_TRIPZINT_0                                             (112U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM3_EPWM_TRIPZINT_0                                             (113U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM4_EPWM_TRIPZINT_0                                             (114U)
#define CSLR_R5FSS1_CORE1_INTR_EHRPWM5_EPWM_TRIPZINT_0                                             (115U)
#define CSLR_R5FSS1_CORE1_INTR_EQEP0_EQEP_INT_0                                                    (116U)
#define CSLR_R5FSS1_CORE1_INTR_EQEP1_EQEP_INT_0                                                    (117U)
#define CSLR_R5FSS1_CORE1_INTR_EQEP2_EQEP_INT_0                                                    (118U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (120U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN0_MCANSS_MCAN_LVL_INT_0                                         (121U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN0_MCANSS_MCAN_LVL_INT_1                                         (122U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (123U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN1_MCANSS_MCAN_LVL_INT_0                                         (124U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN1_MCANSS_MCAN_LVL_INT_1                                         (125U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (126U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN2_MCANSS_MCAN_LVL_INT_0                                         (127U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN2_MCANSS_MCAN_LVL_INT_1                                         (128U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (129U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN3_MCANSS_MCAN_LVL_INT_0                                         (130U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN3_MCANSS_MCAN_LVL_INT_1                                         (131U)
#define CSLR_R5FSS1_CORE1_INTR_MCASP0_REC_INTR_PEND_0                                              (132U)
#define CSLR_R5FSS1_CORE1_INTR_MCASP0_XMIT_INTR_PEND_0                                             (133U)
#define CSLR_R5FSS1_CORE1_INTR_MCASP1_REC_INTR_PEND_0                                              (134U)
#define CSLR_R5FSS1_CORE1_INTR_MCASP1_XMIT_INTR_PEND_0                                             (135U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_LEGACY_PULSE_0                                           (136U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_DOWNSTREAM_PULSE_0                                       (137U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_FLR_PULSE_0                                              (138U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_PHY_LEVEL_0                                              (139U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_LOCAL_LEVEL_0                                            (140U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_ERROR_PULSE_0                                            (141U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_LINK_STATE_PULSE_0                                       (142U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_PWR_STATE_PULSE_0                                        (143U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_PTM_VALID_PULSE_0                                        (144U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_HOT_RESET_PULSE_0                                        (145U)
#define CSLR_R5FSS1_CORE1_INTR_PCIE0_PCIE_CPTS_PEND_0                                              (146U)
#define CSLR_R5FSS1_CORE1_INTR_I2C0_POINTRPEND_0                                                   (150U)
#define CSLR_R5FSS1_CORE1_INTR_I2C1_POINTRPEND_0                                                   (151U)
#define CSLR_R5FSS1_CORE1_INTR_MCSPI0_INTR_SPI_0                                                   (152U)
#define CSLR_R5FSS1_CORE1_INTR_MCSPI1_INTR_SPI_0                                                   (153U)
#define CSLR_R5FSS1_CORE1_INTR_MLB0_MLBSS_MLB_INT_0                                                (154U)
#define CSLR_R5FSS1_CORE1_INTR_MLB0_MLBSS_MLB_AHB_INT_0                                            (155U)
#define CSLR_R5FSS1_CORE1_INTR_MLB0_MLBSS_MLB_AHB_INT_1                                            (156U)
#define CSLR_R5FSS1_CORE1_INTR_UART0_USART_IRQ_0                                                   (158U)
#define CSLR_R5FSS1_CORE1_INTR_UART1_USART_IRQ_0                                                   (159U)
#define CSLR_R5FSS1_CORE1_INTR_UART2_USART_IRQ_0                                                   (160U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER12_INTR_PEND_0                                                 (168U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER13_INTR_PEND_0                                                 (169U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER14_INTR_PEND_0                                                 (170U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER15_INTR_PEND_0                                                 (171U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER16_INTR_PEND_0                                                 (172U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER17_INTR_PEND_0                                                 (173U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER18_INTR_PEND_0                                                 (174U)
#define CSLR_R5FSS1_CORE1_INTR_TIMER19_INTR_PEND_0                                                 (175U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_16                                             (176U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_17                                             (177U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_18                                             (178U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_19                                             (179U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_20                                             (180U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_21                                             (181U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_22                                             (182U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_23                                             (183U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_24                                             (184U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_25                                             (185U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_26                                             (186U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_27                                             (187U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_28                                             (188U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_29                                             (189U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_30                                             (190U)
#define CSLR_R5FSS1_CORE1_INTR_GPIOMUX_INTRTR0_OUTP_31                                             (191U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN4_MCANSS_MCAN_LVL_INT_0                                         (192U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN4_MCANSS_MCAN_LVL_INT_1                                         (193U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (194U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN5_MCANSS_MCAN_LVL_INT_0                                         (195U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN5_MCANSS_MCAN_LVL_INT_1                                         (196U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN5_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (197U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN6_MCANSS_MCAN_LVL_INT_0                                         (198U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN6_MCANSS_MCAN_LVL_INT_1                                         (199U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN6_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (200U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN7_MCANSS_MCAN_LVL_INT_0                                         (201U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN7_MCANSS_MCAN_LVL_INT_1                                         (202U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN7_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (203U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN8_MCANSS_MCAN_LVL_INT_0                                         (204U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN8_MCANSS_MCAN_LVL_INT_1                                         (205U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN8_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (206U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN9_MCANSS_MCAN_LVL_INT_0                                         (207U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN9_MCANSS_MCAN_LVL_INT_1                                         (208U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN9_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                              (209U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN10_MCANSS_MCAN_LVL_INT_0                                        (210U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN10_MCANSS_MCAN_LVL_INT_1                                        (211U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN10_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                             (212U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN11_MCANSS_MCAN_LVL_INT_0                                        (213U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN11_MCANSS_MCAN_LVL_INT_1                                        (214U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN11_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                             (215U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN12_MCANSS_MCAN_LVL_INT_0                                        (216U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN12_MCANSS_MCAN_LVL_INT_1                                        (217U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN12_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                             (218U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN13_MCANSS_MCAN_LVL_INT_0                                        (219U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN13_MCANSS_MCAN_LVL_INT_1                                        (220U)
#define CSLR_R5FSS1_CORE1_INTR_MCAN13_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0                             (221U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_288                                  (224U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_289                                  (225U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_290                                  (226U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_291                                  (227U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_292                                  (228U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_293                                  (229U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_294                                  (230U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_295                                  (231U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_296                                  (232U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_297                                  (233U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_298                                  (234U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_299                                  (235U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_300                                  (236U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_301                                  (237U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_302                                  (238U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_303                                  (239U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_304                                  (240U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_305                                  (241U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_306                                  (242U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_307                                  (243U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_308                                  (244U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_309                                  (245U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_310                                  (246U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_311                                  (247U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_312                                  (248U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_313                                  (249U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_314                                  (250U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_315                                  (251U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_316                                  (252U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_317                                  (253U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_318                                  (254U)
#define CSLR_R5FSS1_CORE1_INTR_NAVSS0_INTR_ROUTER_0_OUTL_INTR_319                                  (255U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_0                                            (256U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_1                                            (257U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_2                                            (258U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_3                                            (259U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_4                                            (260U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_5                                            (261U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_6                                            (262U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_7                                            (263U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_8                                            (264U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_9                                            (265U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_10                                           (266U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_11                                           (267U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_12                                           (268U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_13                                           (269U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_14                                           (270U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_15                                           (271U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_16                                           (272U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_17                                           (273U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_18                                           (274U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_19                                           (275U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_20                                           (276U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_21                                           (277U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_22                                           (278U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_23                                           (279U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_24                                           (280U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_25                                           (281U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_26                                           (282U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_27                                           (283U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_28                                           (284U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_29                                           (285U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_30                                           (286U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_31                                           (287U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_32                                           (288U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_33                                           (289U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_34                                           (290U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_35                                           (291U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_36                                           (292U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_37                                           (293U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_38                                           (294U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_39                                           (295U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_40                                           (296U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_41                                           (297U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_42                                           (298U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_43                                           (299U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_44                                           (300U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_45                                           (301U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_46                                           (302U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_47                                           (303U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_48                                           (304U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_49                                           (305U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_50                                           (306U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_51                                           (307U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_52                                           (308U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_53                                           (309U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_54                                           (310U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_55                                           (311U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_56                                           (312U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_57                                           (313U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_58                                           (314U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_59                                           (315U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_60                                           (316U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_61                                           (317U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_62                                           (318U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_63                                           (319U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_64                                           (320U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_65                                           (321U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_66                                           (322U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_67                                           (323U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_68                                           (324U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_69                                           (325U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_70                                           (326U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_71                                           (327U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_72                                           (328U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_73                                           (329U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_74                                           (330U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_75                                           (331U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_76                                           (332U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_77                                           (333U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_78                                           (334U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_79                                           (335U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_80                                           (336U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_81                                           (337U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_82                                           (338U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_83                                           (339U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_84                                           (340U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_85                                           (341U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_86                                           (342U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_87                                           (343U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_88                                           (344U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_89                                           (345U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_90                                           (346U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_91                                           (347U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_92                                           (348U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_93                                           (349U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_94                                           (350U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_95                                           (351U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_96                                           (352U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_97                                           (353U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_98                                           (354U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_99                                           (355U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_100                                          (356U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_101                                          (357U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_102                                          (358U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_103                                          (359U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_104                                          (360U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_105                                          (361U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_106                                          (362U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_107                                          (363U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_108                                          (364U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_109                                          (365U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_110                                          (366U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_111                                          (367U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_112                                          (368U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_113                                          (369U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_114                                          (370U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_115                                          (371U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_116                                          (372U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_117                                          (373U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_118                                          (374U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_119                                          (375U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_120                                          (376U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_121                                          (377U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_122                                          (378U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_123                                          (379U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_124                                          (380U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_125                                          (381U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_126                                          (382U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_127                                          (383U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_128                                          (384U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_129                                          (385U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_130                                          (386U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_131                                          (387U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_132                                          (388U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_133                                          (389U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_134                                          (390U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_135                                          (391U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_136                                          (392U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_137                                          (393U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_138                                          (394U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_139                                          (395U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_140                                          (396U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_141                                          (397U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_142                                          (398U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_143                                          (399U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_144                                          (400U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_145                                          (401U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_146                                          (402U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_147                                          (403U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_148                                          (404U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_149                                          (405U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_150                                          (406U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_151                                          (407U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_152                                          (408U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_153                                          (409U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_154                                          (410U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_155                                          (411U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_156                                          (412U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_157                                          (413U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_158                                          (414U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_159                                          (415U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_160                                          (416U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_161                                          (417U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_162                                          (418U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_163                                          (419U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_164                                          (420U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_165                                          (421U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_166                                          (422U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_167                                          (423U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_168                                          (424U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_169                                          (425U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_170                                          (426U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_171                                          (427U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_172                                          (428U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_173                                          (429U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_174                                          (430U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_175                                          (431U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_176                                          (432U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_177                                          (433U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_178                                          (434U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_179                                          (435U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_180                                          (436U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_181                                          (437U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_182                                          (438U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_183                                          (439U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_184                                          (440U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_185                                          (441U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_186                                          (442U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_187                                          (443U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_188                                          (444U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_189                                          (445U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_190                                          (446U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_191                                          (447U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_192                                          (448U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_193                                          (449U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_194                                          (450U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_195                                          (451U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_196                                          (452U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_197                                          (453U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_198                                          (454U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_199                                          (455U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_200                                          (456U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_201                                          (457U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_202                                          (458U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_203                                          (459U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_204                                          (460U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_205                                          (461U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_206                                          (462U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_207                                          (463U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_208                                          (464U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_209                                          (465U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_210                                          (466U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_211                                          (467U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_212                                          (468U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_213                                          (469U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_214                                          (470U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_215                                          (471U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_216                                          (472U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_217                                          (473U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_218                                          (474U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_219                                          (475U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_220                                          (476U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_221                                          (477U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_222                                          (478U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_223                                          (479U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_224                                          (480U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_225                                          (481U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_226                                          (482U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_227                                          (483U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_228                                          (484U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_229                                          (485U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_230                                          (486U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_231                                          (487U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_232                                          (488U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_233                                          (489U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_234                                          (490U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_235                                          (491U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_236                                          (492U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_237                                          (493U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_238                                          (494U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_239                                          (495U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_240                                          (496U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_241                                          (497U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_242                                          (498U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_243                                          (499U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_244                                          (500U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_245                                          (501U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_246                                          (502U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_247                                          (503U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_248                                          (504U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_249                                          (505U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_250                                          (506U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_251                                          (507U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_252                                          (508U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_253                                          (509U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_254                                          (510U)
#define CSLR_R5FSS1_CORE1_INTR_R5FSS1_INTROUTER0_OUTL_255                                          (511U)

#ifdef __cplusplus
}
#endif
#endif /* CSLR_R5FSS1_CORE1_INTERRUPT_MAP_H_ */

