Problems with VHDL code generation
Hello!

I'm trying to utilize the VHDL Generator for a HW Design. The Verilog Generator seems to work fine, but I keep getting the following error messages.

```
VLNV: ::: was not found in library.
VLNV: ::: was not found in library.
The design ::: referenced in component <the HW Design component> was not found in library
```

So, from my limited understanding, the component ending with "*.design" is what the error message is referencing. However, even after looking at the XMLs directly, I can't figure out what's missing.

Any amount of assistance would be appreciated!

EDIT:

After close examination, it appears there's a field under HW Component -> Views -> hierarchical -> Design instantiation that's not getting filled with the design. It feels as though this field should get populated? Any hints on how to set the field from the tool?