Formally Verified Verilog Reasoning Datasets
William Patrick Yubeaton
wilyub
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models 0
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datasets 9
wilyub/VeriThoughtsTrainSetInconsistentReasoningGT
Viewer • Updated • 10.1k • 14
wilyub/VeriThoughtsTrainSetInconsistentReasoningGEN
Viewer • Updated • 10.1k • 21
wilyub/VeriThoughtsTrainSetInconsistentInstructionGT
Viewer • Updated • 10.1k • 19
wilyub/VeriThoughtsTrainSetInconsistentInstructionGEN
Viewer • Updated • 10.1k • 28
wilyub/VeriThoughtsTrainSetConsistentReasoning
Viewer • Updated • 10.1k • 35
wilyub/VeriThoughtsTrainSetConsistentInstruction
Viewer • Updated • 10.1k • 26
wilyub/VeriThoughtsTrainSet
Viewer • Updated • 20.2k • 135 • 1
wilyub/VeriThoughtsBenchmark
Viewer • Updated • 291 • 36
wilyub/VeriThoughts-30K
Viewer • Updated • 30.3k • 40